Converting from RGB to YCbCr takes one less stage than converting
from YCbCr to RGB color space.
Moving extra delay stage(5), of the sync signals to a particular
YCbCr to RGB color space conversion case.
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
Define INPUT_PIPELINE parameter, which can be used to activate the
REGISTER_INPUTS parameter of the PHY. This parameter will add an
additional register stage into the incoming parallel data stream.
It can be used to relax the timing margin between the PHY and Link modules.
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
This patch contains an initial effort to support the Stratix 10
architecture in our JESD204 framework.
Several instances were updated, doing simple context switching using the
DEVICE_FAMILY system parameter:
- xcvr_reset_control
- lane PLL (ATX PLL)
- link PLL (fPLL)
- native XCVR instance
Apart from the slightly different parameters of the instances above,
there were small differences at the reconfiguration Avalon_MM interface.
The link_pll_reset_control is required just for Arria10, so in case of
Stratix10 it isn't instantiated.
In Stratix 10 architecture there are several additional ports of the
xcvr_reset_control module that must be connected to the native XCVR
instance or tied to GND.
The following xcvr_reset_control ports were defined and connected to the
XCVR:
- rx|tx_analogreset_stat
- rx|tx_digitalreset_stat
- pll_select
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
If dac_valid is not a constant '1' it gets synchronized with the
dac_data_sync signal. This causes that dac_valid never asserts while
dac_data_sync is high, this way skipping the phase initialization.
ADRV9001 interfacing IP supports the following modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 32 80 80 2.5 SDR 8
CSSI__1-lane 1 32 160 80 5 DDR 4
CSSI__4-lane 4 8 80 80 10 SDR 2
CSSI__4-lane 4 8 160 80 20 DDR 1
LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4
LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface
Intel devices supports only CSSI modes.
De-assert dac_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
De-assert adc_rst together with an updated control set.
This allows writing the control registers before releasing the reset.
This is important at start-up when stable set of controls is required.
Allow monitoring of non-PN patterns which have zeros in it.
e.g. nible-ramp, full range ramp.
Singular zeros got ignored if not out of sync, while OOS_THRESHOLD
consecutive zeros or non-matching data asserts the out of sync line.
Fix the *_ip.tcl scripts for axi_spi_engine and spi_engine_offload
module.
In case of a bool parameters the value_format and value properties must
be set for both user and hdl paramters. If not, in the generated verilog
code the tool will use "true" or "false" strings, instead of 0 or 1.
AndreiGrozav
Istvan Csomortani
Dragos Bogdan
Stanca Pop
Laszlo Nagy
Adrian Costina
Rodrigo Alencar