Allow the top level files to have parameters.
Pass the parameters from system_project.tcl to the Vivado/Quartus project and
to the block design scripts through ad_project_params variable.
Usage:
1. create a project with a list of parameters:
adi_project_xilinx my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
or
adi_project_altera my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
2. access the parameter in QSYS or block design through the $ad_project_params variable
e.g
set PARAM_A $ad_project_params(PARAM_A)
set PARAM_B $ad_project_params(PARAM_B)
3. In system_top.v use PARAM_A and PARAM_B as parameters/generics
Look for undefined clocks which do not show up in the timing summary
therefore can lead to silent failures.
If clocks are not defined they are not analyzed during the timing
checks.
The scripts are looking for a previous run result, a routed design
checkpoint to use it as a reference during the incremental build flow.
Before clearing the project files, the scrips will save the reference dcp
file in the project folder.
If the reference dcp does not exists the build continues normally.
Proposed workflow:
1. Build your project normally with 'make' or place manually a
reference.dcp file in the Vivado project folder.
2. Do some minor modifications
3. Run the make with the following option:
make MODE=incr
4. Repeat steps 2-3
Using a common IP cache location for all the project will speed up
compile time of common blocks used in base designs. Example a MicroBlaze
core for VCU118 once compiled it will be reused on other projects.
Using a common IP cache will speed up re-compiles of every project in OOC
mode since the cache won't be cleared as with normal compile flow.
To reduce compilation time use default stratagies for synthesis and
implementation. If a project will require custom strategies, enable it
just for that particular project.
This modification will affect both Intel and Xilinx projects.
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
Laszlo Nagy
Sergiu Arpadi
Adrian Costina
AndreiGrozav
Rejeesh Kutty
Shrutika Redkar
Lars-Peter Clausen