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Add LICENSE_ADIJESD204. Delete jesd204/README.md 

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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Iulia Moldovan 2023-08-17 15:16:18 +03:00 committed by imoldovan
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library/jesd204/README.md → LICENSE_ADIJESD204
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@ -1,6 +1,4 @@
# Analog Devices JESD204B HDL Support
## Licensing
SPDX short identifier: ADIJESD204
The ADI JESD204 Core is released under the following license, which is
different than all other HDL cores in this repository.
@ -8,7 +6,7 @@ different than all other HDL cores in this repository.
Please read this, and understand the freedoms and responsibilities you have by
using this source code/core.
The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
The JESD204 HDL, is copyright (c) 2016-2023 Analog Devices Inc.
This core is free software, you can use run, copy, study, change, ask questions
about and improve this core. Distribution of source, or resulting binaries
@ -22,13 +20,13 @@ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License version 2
along with this source code, and binary. If not, see
along with this source code, and binary. If not, see
<http://www.gnu.org/licenses/>.
Commercial licenses (with commercial support) of this JESD204 core are also
available under terms different than the General Public License. (e.g. they do
available under terms different than the General Public License (e.g. they do
not require you to accompany any image (FPGA or ASIC) using the JESD204 core
with any corresponding source code.) For these alternate terms you must
with any corresponding source code). For these alternate terms you must
purchase a license from Analog Devices Technology Licensing Office. Users
interested in such a license should contact jesd204-licensing@analog.com for
more information. This commercial license is sub-licensable (if you purchase
@ -39,24 +37,6 @@ to use this core in a commercial setting without releasing their source code).
In addition, we kindly ask you to acknowledge ADI in any program, application
or publication in which you use this JESD204 HDL core. (You are not required to
do so; it is up to your common sense to decide whether you want to comply with
this request or not.) For general publications, we suggest referencing : “The
this request or not.) For general publications, we suggest referencing: "The
design and implementation of the JESD204 HDL Core used in this project is
copyright © 2016-2023, Analog Devices, Inc.”
## Support
Analog Devices will provide limited online support for anyone using the core
with Analog Devices components (ADC, DAC, Clock, etc) via
https://ez.analog.com/community/fpga under the GPL license. If you would like
deterministic support when using this core with an ADI component, please
investigate a commercial license. Using a non-ADI JESD204 device with this core
is possible under the GPL, but Analog Devices will not help with issues you may
encounter.
## Documenation
- [JESD204B/C overview](https://wiki.analog.com/resources/fpga/peripherals/jesd204)
- [Analog Devices JESD204B/C Transmit Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx)
- [Analog Devices JESD204B/C Receive Peripheral](https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx)
copyright (c) 2016-2023, Analog Devices, Inc."