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axi_ad9361- altera/xilinx reconcile- may be broken- do not use

main
Rejeesh Kutty 2017-07-24 16:28:40 -04:00
parent b65802ee1e
commit ff50963c7f
5 changed files with 635 additions and 552 deletions
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2
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
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@ -318,7 +318,7 @@ module axi_ad9361_lvds_if #(
if (rx_frame_d == rx_frame_s) begin if (rx_frame_d == rx_frame_s) begin
adc_status_p <= locked_s; adc_status_p <= locked_s;
end else begin end else begin
adc_status_p <= 1'b1; adc_status_p <= 1'b0;
end end
end end

14
library/axi_ad9361/axi_ad9361.v
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@ -311,10 +311,6 @@ module axi_ad9361 #(
assign tx_data_out_p = 6'h00; assign tx_data_out_p = 6'h00;
assign tx_data_out_n = 6'h3f; assign tx_data_out_n = 6'h3f;
assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd1;
axi_ad9361_cmos_if #( axi_ad9361_cmos_if #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
@ -345,6 +341,7 @@ module axi_ad9361 #(
.tdd_mode (tdd_mode_s), .tdd_mode (tdd_mode_s),
.mmcm_rst (mmcm_rst), .mmcm_rst (mmcm_rst),
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn),
.up_enable (up_enable), .up_enable (up_enable),
.up_txnrx (up_txnrx), .up_txnrx (up_txnrx),
.up_adc_dld (up_adc_dld_s), .up_adc_dld (up_adc_dld_s),
@ -355,7 +352,14 @@ module axi_ad9361 #(
.up_dac_drdata (up_dac_drdata_s), .up_dac_drdata (up_dac_drdata_s),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked_s)); .delay_locked (delay_locked_s),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked(up_drp_locked));
end end
endgenerate endgenerate

9
library/axi_ad9361/axi_ad9361_ip.tcl
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@ -6,12 +6,9 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9361 adi_ip_create axi_ad9361
adi_ip_files axi_ad9361 [list \ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_cmos_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \

480
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
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@ -66,9 +66,9 @@ module axi_ad9361_cmos_if #(
// receive data path interface // receive data path interface
output reg adc_valid, output adc_valid,
output reg [47:0] adc_data, output [47:0] adc_data,
output reg adc_status, output adc_status,
input adc_r1_mode, input adc_r1_mode,
input adc_ddr_edgesel, input adc_ddr_edgesel,
@ -89,6 +89,7 @@ module axi_ad9361_cmos_if #(
input mmcm_rst, input mmcm_rst,
input up_clk, input up_clk,
input up_rstn,
input up_enable, input up_enable,
input up_txnrx, input up_txnrx,
input [12:0] up_adc_dld, input [12:0] up_adc_dld,
@ -99,42 +100,47 @@ module axi_ad9361_cmos_if #(
output [79:0] up_dac_drdata, output [79:0] up_dac_drdata,
input delay_clk, input delay_clk,
input delay_rst, input delay_rst,
output delay_locked); output delay_locked,
// drp interface
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// internal registers // internal registers
reg [ 1:0] rx_frame = 0; reg adc_r1_mode_n = 'd0;
reg [11:0] rx_data_p = 0; reg rx_r1_mode = 'd0;
reg rx_error_r1 = 'd0; reg rx_locked_m1 = 'd0;
reg rx_valid_r1 = 'd0; reg rx_locked = 'd0;
reg [23:0] rx_data_r1 = 'd0; reg [ 1:0] rx_frame = 'd0;
reg rx_error_r2 = 'd0; reg [11:0] rx_data_1 = 'd0;
reg rx_valid_r2 = 'd0; reg adc_valid_p = 'd0;
reg [47:0] rx_data_r2 = 'd0; reg [47:0] adc_data_p = 'd0;
reg adc_p_valid = 'd0; reg adc_status_p = 'd0;
reg [47:0] adc_p_data = 'd0; reg adc_valid_n = 'd0;
reg adc_p_status = 'd0; reg [47:0] adc_data_n = 'd0;
reg adc_n_valid = 'd0; reg adc_status_n = 'd0;
reg [47:0] adc_n_data = 'd0;
reg adc_n_status = 'd0;
reg adc_valid_int = 'd0; reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0; reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0; reg adc_status_int = 'd0;
reg [ 1:0] tx_data_cnt = 'd0; reg [ 1:0] tx_clk_p = 'd0;
reg [47:0] tx_data = 'd0; reg [ 1:0] tx_frame_p = 'd0;
reg tx_frame_p = 'd0; reg [11:0] tx_data_0_p = 'd0;
reg tx_frame_n = 'd0; reg [11:0] tx_data_1_p = 'd0;
reg [11:0] tx_data_p = 'd0; reg [ 1:0] tx_clk_n = 'd0;
reg [11:0] tx_data_n = 'd0; reg [ 1:0] tx_frame_n = 'd0;
reg tx_n_frame_p = 'd0; reg [11:0] tx_data_0_n = 'd0;
reg tx_n_frame_n = 'd0; reg [11:0] tx_data_1_n = 'd0;
reg [11:0] tx_n_data_p = 'd0; reg [ 1:0] tx_clk = 'd0;
reg [11:0] tx_n_data_n = 'd0; reg [ 1:0] tx_frame = 'd0;
reg tx_p_frame_p = 'd0; reg [11:0] tx_data_0 = 'd0;
reg tx_p_frame_n = 'd0; reg [11:0] tx_data_1 = 'd0;
reg [11:0] tx_p_data_p = 'd0;
reg [11:0] tx_p_data_n = 'd0;
reg up_enable_int = 'd0; reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0; reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0; reg enable_up_m1 = 'd0;
@ -143,158 +149,173 @@ module axi_ad9361_cmos_if #(
reg txnrx_up = 'd0; reg txnrx_up = 'd0;
reg enable_int = 'd0; reg enable_int = 'd0;
reg txnrx_int = 'd0; reg txnrx_int = 'd0;
reg enable_n_int = 'd0; reg enable_int_n = 'd0;
reg txnrx_n_int = 'd0; reg txnrx_int_n = 'd0;
reg enable_p_int = 'd0; reg enable_int_p = 'd0;
reg txnrx_p_int = 'd0; reg txnrx_int_p = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals // internal signals
wire [11:0] rx_data_1_s;
wire [11:0] rx_data_0_s;
wire [ 1:0] rx_frame_s; wire [ 1:0] rx_frame_s;
wire [ 3:0] rx_frame_4_s;
wire [ 2:0] tx_data_sel_s;
wire [11:0] rx_data_p_s;
wire [11:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s; wire locked_s;
genvar l_inst; // drp interface signals
// receive data path interface assign up_drp_rdata = 32'd0;
assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd1;
assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s}; // r1mode
assign rx_frame_4_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin
rx_frame <= rx_frame_s;
rx_data_p <= rx_data_p_s;
end
// receive data path for single rf, frame is expected to qualify i only
always @(posedge l_clk) begin
rx_error_r1 <= ~^ rx_frame_s;
rx_valid_r1 <= ^ rx_frame_s;
case (rx_frame_s)
2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p};
default: rx_data_r1 <= 24'd0;
endcase
end
// receive data path for dual rf, frame is expected to qualify iq for rf-1 only
always @(posedge l_clk) begin
rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) ||
(rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1;
rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) ||
(rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0;
case (rx_frame_s)
2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s};
2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[23: 0] <= rx_data_r2[23: 0];
endcase
case (rx_frame_s)
2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s};
2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p};
default: rx_data_r2[47:24] <= rx_data_r2[47:24];
endcase
end
// receive data path mux
always @(posedge l_clk) begin
if (adc_r1_mode == 1'b1) begin
adc_p_valid <= rx_valid_r1;
adc_p_data <= {24'd0, rx_data_r1};
adc_p_status <= ~rx_error_r1;
end else begin
adc_p_valid <= rx_valid_r2;
adc_p_data <= rx_data_r2;
adc_p_status <= ~rx_error_r2;
end
end
// transfer to a synchronous common clock
always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid;
adc_n_data <= adc_p_data;
adc_n_status <= adc_p_status;
end
always @(posedge clk) begin
adc_valid_int <= adc_n_valid;
adc_data_int <= adc_n_data;
adc_status_int <= adc_n_status;
adc_valid <= adc_valid_int;
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int & locked;
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 2'b10;
end else if (tx_data_cnt[1] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data <= dac_data;
end
case (tx_data_sel_s)
3'b101: begin
tx_frame_p <= 1'b0;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[35:24];
tx_data_n <= tx_data[47:36];
end
3'b100: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b1;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
3'b110: begin
tx_frame_p <= 1'b1;
tx_frame_n <= 1'b0;
tx_data_p <= tx_data[11: 0];
tx_data_n <= tx_data[23:12];
end
default: begin
tx_frame_p <= 1'd0;
tx_frame_n <= 1'd0;
tx_data_p <= 12'd0;
tx_data_n <= 12'd0;
end
endcase
end
// transfer data from a synchronous clock (skew less than 2ns)
always @(negedge clk) begin always @(negedge clk) begin
tx_n_frame_p <= tx_frame_p; adc_r1_mode_n <= adc_r1_mode;
tx_n_frame_n <= tx_frame_n;
tx_n_data_p <= tx_data_p;
tx_n_data_n <= tx_data_n;
end end
always @(posedge l_clk) begin always @(posedge l_clk) begin
tx_p_frame_p <= tx_n_frame_p; rx_r1_mode <= adc_r1_mode_n;
tx_p_frame_n <= tx_n_frame_n; end
tx_p_data_p <= tx_n_data_p;
tx_p_data_n <= tx_n_data_n; // adc-status
assign delay_locked = locked_s;
always @(posedge l_clk) begin
rx_locked_m1 <= locked_s;
rx_locked <= rx_locked_m1;
end
// frame check
always @(posedge l_clk) begin
if (rx_r1_mode == 1'd1) begin
rx_frame <= rx_frame_s;
end else begin
rx_frame <= ~rx_frame_s;
end
end
// data hold
always @(posedge l_clk) begin
rx_data_1 <= rx_data_1_s;
end
// delineation
always @(posedge l_clk) begin
case ({rx_r1_mode, rx_frame_s})
3'b011: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
end
3'b000: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= {rx_data_1_s, rx_data_0_s};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
3'b001: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
end
3'b010: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= {rx_data_0_s, rx_data_1};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
3'b110: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
end
3'b101: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
end
default: begin
adc_valid_p <= 1'b0;
adc_data_p <= 48'd0;
end
endcase
end
// adc-status
always @(posedge l_clk) begin
if (rx_frame == rx_frame_s) begin
adc_status_p <= rx_locked;
end else begin
adc_status_p <= 1'b0;
end
end
// transfer to common clock
always @(negedge l_clk) begin
adc_valid_n <= adc_valid_p;
adc_data_n <= adc_data_p;
adc_status_n <= adc_status_p;
end
assign adc_valid = adc_valid_int;
assign adc_data = adc_data_int;
assign adc_status = adc_status_int;
always @(posedge clk) begin
adc_valid_int <= adc_valid_n;
adc_data_int <= adc_data_n;
adc_status_int <= adc_status_n;
end
// dac-tx interface
always @(posedge clk) begin
tx_clk_p <= {dac_clksel, ~dac_clksel};
end
always @(posedge clk) begin
case ({dac_r1_mode, dac_valid})
3'b00: begin
tx_frame_p <= 2'b00;
tx_data_0_p <= dac_data[35:24];
tx_data_1_p <= dac_data[47:36];
end
2'b01: begin
tx_frame_p <= 2'b11;
tx_data_0_p <= dac_data[11:0];
tx_data_1_p <= dac_data[23:12];
end
2'b11: begin
tx_frame_p <= 2'b01;
tx_data_0_p <= dac_data[11:0];
tx_data_1_p <= dac_data[23:12];
end
default: begin
tx_frame_p <= 2'd0;
tx_data_0_p <= 12'd0;
tx_data_1_p <= 12'd0;
end
endcase
end
// transfer to local clock
always @(negedge clk) begin
tx_clk_n <= tx_clk_p;
tx_frame_n <= tx_frame_p;
tx_data_0_n <= tx_data_0_p;
tx_data_1_n <= tx_data_1_p;
end
always @(posedge l_clk) begin
tx_clk <= tx_clk_n;
tx_frame <= tx_frame_n;
tx_data_0 <= tx_data_0_n;
tx_data_1 <= tx_data_1_n;
end end
// tdd/ensm control // tdd/ensm control
@ -329,37 +350,35 @@ module axi_ad9361_cmos_if #(
end end
always @(negedge clk) begin always @(negedge clk) begin
enable_n_int <= enable_int; enable_int_n <= enable_int;
txnrx_n_int <= txnrx_int; txnrx_int_n <= txnrx_int;
end end
always @(posedge l_clk) begin always @(posedge l_clk) begin
enable_p_int <= enable_n_int; enable_int_p <= enable_int_n;
txnrx_p_int <= txnrx_n_int; txnrx_int_p <= txnrx_int_n;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end end
// receive data interface, ibuf -> idelay -> iddr // receive data interface, ibuf -> idelay -> iddr
genvar i;
generate generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data for (i = 0; i < 12; i = i + 1) begin: g_rx_data
ad_cmos_in #( ad_data_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data ( i_rx_data (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in (rx_data_in[l_inst]), .rx_data_in_p (rx_data_in[i]),
.rx_data_p (rx_data_p_s[l_inst]), .rx_data_in_n (1'd0),
.rx_data_n (rx_data_n_s[l_inst]), .rx_data_p (rx_data_1_s[i]),
.rx_data_n (rx_data_0_s[i]),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]), .up_dld (up_adc_dld[i]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
@ -368,41 +387,45 @@ module axi_ad9361_cmos_if #(
// receive frame interface, ibuf -> idelay -> iddr // receive frame interface, ibuf -> idelay -> iddr
ad_cmos_in #( ad_data_in #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_frame ( i_rx_frame (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in (rx_frame_in), .rx_data_in_p (rx_frame_in),
.rx_data_p (rx_frame_p_s), .rx_data_in_n (1'd0),
.rx_data_n (rx_frame_n_s), .rx_data_p (rx_frame_s[1]),
.rx_data_n (rx_frame_s[0]),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_adc_dld[12]), .up_dld (up_adc_dld[12]),
.up_dwdata (up_adc_dwdata[64:60]), .up_dwdata (up_adc_dwdata[64:60]),
.up_drdata (up_adc_drdata[64:60]), .up_drdata (up_adc_drdata[64:60]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked)); .delay_locked (locked_s));
// transmit data interface, oddr -> obuf // transmit data interface, oddr -> obuf
generate generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data for (i = 0; i < 12; i = i + 1) begin: g_tx_data
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data ( i_tx_data (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]), .tx_data_p (tx_data_1[i]),
.tx_data_n (tx_p_data_n[l_inst]), .tx_data_n (tx_data_0[i]),
.tx_data_out (tx_data_out[l_inst]), .tx_data_out_p (tx_data_out[i]),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]), .up_dld (up_dac_dld[i]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
@ -411,16 +434,18 @@ module axi_ad9361_cmos_if #(
// transmit frame interface, oddr -> obuf // transmit frame interface, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame ( i_tx_frame (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_p_frame_p), .tx_data_p (tx_frame[1]),
.tx_data_n (tx_p_frame_n), .tx_data_n (tx_frame[0]),
.tx_data_out (tx_frame_out), .tx_data_out_p (tx_frame_out),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[12]), .up_dld (up_dac_dld[12]),
.up_dwdata (up_dac_dwdata[64:60]), .up_dwdata (up_dac_dwdata[64:60]),
@ -431,16 +456,18 @@ module axi_ad9361_cmos_if #(
// transmit clock interface, oddr -> obuf // transmit clock interface, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk ( i_tx_clk (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (dac_clkdata_p), .tx_data_p (tx_clk[1]),
.tx_data_n (dac_clkdata_n), .tx_data_n (tx_clk[0]),
.tx_data_out (tx_clk_out), .tx_data_out_p (tx_clk_out),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[13]), .up_dld (up_dac_dld[13]),
.up_dwdata (up_dac_dwdata[69:65]), .up_dwdata (up_dac_dwdata[69:65]),
@ -451,16 +478,18 @@ module axi_ad9361_cmos_if #(
// enable, oddr -> obuf // enable, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_enable ( i_enable (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (enable_p_int), .tx_data_p (enable_int_p),
.tx_data_n (enable_p_int), .tx_data_n (enable_int_p),
.tx_data_out (enable), .tx_data_out_p (enable),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[14]), .up_dld (up_dac_dld[14]),
.up_dwdata (up_dac_dwdata[74:70]), .up_dwdata (up_dac_dwdata[74:70]),
@ -471,16 +500,18 @@ module axi_ad9361_cmos_if #(
// txnrx, oddr -> obuf // txnrx, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_txnrx ( i_txnrx (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (txnrx_p_int), .tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_p_int), .tx_data_n (txnrx_int_p),
.tx_data_out (txnrx), .tx_data_out_p (txnrx),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[15]), .up_dld (up_dac_dld[15]),
.up_dwdata (up_dac_dwdata[79:75]), .up_dwdata (up_dac_dwdata[79:75]),
@ -491,17 +522,14 @@ module axi_ad9361_cmos_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
always @(posedge clk) begin ad_data_clk #(
locked_m1 <= locked_s; .SINGLE_ENDED (1),
locked <= locked_m1;
end
ad_cmos_clk #(
.DEVICE_TYPE (DEVICE_TYPE)) .DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (mmcm_rst), .rst (1'd0),
.locked (locked_s), .locked (),
.clk_in (rx_clk_in), .clk_in_p (rx_clk_in),
.clk_in_n (1'd0),
.clk (l_clk)); .clk (l_clk));
endmodule endmodule

498
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -72,9 +72,9 @@ module axi_ad9361_lvds_if #(
// receive data path interface // receive data path interface
output reg adc_valid, output adc_valid,
output reg [47:0] adc_data, output [47:0] adc_data,
output reg adc_status, output adc_status,
input adc_r1_mode, input adc_r1_mode,
input adc_ddr_edgesel, input adc_ddr_edgesel,
@ -108,7 +108,7 @@ module axi_ad9361_lvds_if #(
input delay_rst, input delay_rst,
output delay_locked, output delay_locked,
//drp interface // drp interface
input up_drp_sel, input up_drp_sel,
input up_drp_wr, input up_drp_wr,
@ -118,44 +118,43 @@ module axi_ad9361_lvds_if #(
output up_drp_ready, output up_drp_ready,
output up_drp_locked); output up_drp_locked);
// internal registers // internal registers
reg [ 5:0] rx_data_p = 0; reg adc_r1_mode_n = 'd0;
reg rx_frame_p = 0; reg rx_r1_mode = 'd0;
reg [ 1:0] rx_ccnt = 0; reg rx_locked_m1 = 'd0;
reg rx_calign = 0; reg rx_locked = 'd0;
reg rx_align = 0; reg rx_valid = 'd0;
reg [11:0] rx_data = 'd0;
reg [ 1:0] rx_frame = 'd0; reg [ 1:0] rx_frame = 'd0;
reg [11:0] rx_data_d = 'd0; reg [ 5:0] rx_data_1 = 'd0;
reg [ 1:0] rx_frame_d = 'd0; reg [ 5:0] rx_data_0 = 'd0;
reg rx_error_r1 = 'd0; reg [ 3:0] rx_frame_d = 'd0;
reg rx_valid_r1 = 'd0; reg [ 5:0] rx_data_1_2d = 'd0;
reg [23:0] rx_data_r1 = 'd0; reg [ 5:0] rx_data_0_2d = 'd0;
reg rx_error_r2 = 'd0; reg [ 5:0] rx_data_1_d = 'd0;
reg rx_valid_r2 = 'd0; reg adc_valid_p = 'd0;
reg [47:0] rx_data_r2 = 'd0; reg [47:0] adc_data_p = 'd0;
reg adc_p_valid = 'd0; reg adc_status_p = 'd0;
reg [47:0] adc_p_data = 'd0; reg adc_valid_n = 'd0;
reg adc_p_status = 'd0; reg [47:0] adc_data_n = 'd0;
reg adc_n_valid = 'd0; reg adc_status_n = 'd0;
reg [47:0] adc_n_data = 'd0;
reg adc_n_status = 'd0;
reg adc_valid_int = 'd0; reg adc_valid_int = 'd0;
reg [47:0] adc_data_int = 'd0; reg [47:0] adc_data_int = 'd0;
reg adc_status_int = 'd0; reg adc_status_int = 'd0;
reg [ 2:0] tx_data_cnt = 'd0; reg [ 1:0] tx_data_sel = 'd0;
reg [47:0] tx_data = 'd0; reg [47:0] tx_data = 'd0;
reg [ 1:0] tx_clk_p = 'd0;
reg tx_frame_p = 'd0;
reg [ 5:0] tx_data_0_p = 'd0;
reg [ 5:0] tx_data_1_p = 'd0;
reg [ 1:0] tx_clk_n = 'd0;
reg tx_frame_n = 'd0;
reg [ 5:0] tx_data_0_n = 'd0;
reg [ 5:0] tx_data_1_n = 'd0;
reg [ 1:0] tx_clk = 'd0;
reg tx_frame = 'd0; reg tx_frame = 'd0;
reg [ 5:0] tx_data_p = 'd0; reg [ 5:0] tx_data_0 = 'd0;
reg [ 5:0] tx_data_n = 'd0; reg [ 5:0] tx_data_1 = 'd0;
reg tx_n_frame = 'd0;
reg [ 5:0] tx_n_data_p = 'd0;
reg [ 5:0] tx_n_data_n = 'd0;
reg tx_p_frame = 'd0;
reg [ 5:0] tx_p_data_p = 'd0;
reg [ 5:0] tx_p_data_n = 'd0;
reg up_enable_int = 'd0; reg up_enable_int = 'd0;
reg up_txnrx_int = 'd0; reg up_txnrx_int = 'd0;
reg enable_up_m1 = 'd0; reg enable_up_m1 = 'd0;
@ -164,24 +163,16 @@ module axi_ad9361_lvds_if #(
reg txnrx_up = 'd0; reg txnrx_up = 'd0;
reg enable_int = 'd0; reg enable_int = 'd0;
reg txnrx_int = 'd0; reg txnrx_int = 'd0;
reg enable_n_int = 'd0; reg enable_int_n = 'd0;
reg txnrx_n_int = 'd0; reg txnrx_int_n = 'd0;
reg enable_p_int = 'd0; reg enable_int_p = 'd0;
reg txnrx_p_int = 'd0; reg txnrx_int_p = 'd0;
reg dac_clkdata_p = 'd0;
reg dac_clkdata_n = 'd0;
reg locked_m1 = 'd0;
reg locked = 'd0;
// internal signals // internal signals
wire rx_align_s; wire [ 5:0] rx_data_1_s;
wire [ 3:0] rx_frame_s; wire [ 5:0] rx_data_0_s;
wire [ 3:0] tx_data_sel_s; wire [ 1:0] rx_frame_s;
wire [ 5:0] rx_data_p_s;
wire [ 5:0] rx_data_n_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire locked_s; wire locked_s;
// drp interface signals // drp interface signals
@ -190,174 +181,245 @@ module axi_ad9361_lvds_if #(
assign up_drp_ready = 1'd0; assign up_drp_ready = 1'd0;
assign up_drp_locked = 1'd1; assign up_drp_locked = 1'd1;
genvar l_inst; // r1mode
// receive data path interface always @(negedge clk) begin
adc_r1_mode_n <= adc_r1_mode;
assign rx_align_s = rx_frame_n_s ^ rx_frame_p_s; end
always @(posedge l_clk) begin always @(posedge l_clk) begin
rx_data_p <= rx_data_p_s; rx_r1_mode <= adc_r1_mode_n;
rx_frame_p <= rx_frame_p_s; end
rx_ccnt <= rx_ccnt + 1'b1;
if (rx_ccnt == 2'd0) begin // adc-status
rx_calign <= rx_align;
rx_align <= rx_align_s; assign delay_locked = locked_s;
always @(posedge l_clk) begin
rx_locked_m1 <= locked_s;
rx_locked <= rx_locked_m1;
end
// altera-equivalence
always @(posedge l_clk) begin
rx_valid <= ~rx_valid;
rx_frame <= rx_frame_s;
rx_data_1 <= rx_data_1_s;
rx_data_0 <= rx_data_0_s;
end
// frame check
always @(posedge l_clk) begin
if (rx_valid == 1'd1) begin
if (rx_r1_mode == 1'd1) begin
rx_frame_d <= {rx_frame_s, rx_frame};
end else begin end else begin
rx_calign <= rx_calign; rx_frame_d <= {~rx_frame_s, ~rx_frame};
rx_align <= rx_align | rx_align_s; end
end end
end end
assign rx_frame_s = {rx_frame_d, rx_frame}; // data hold
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_calign == 1'b1) begin if (rx_valid == 1'd1) begin
rx_data <= {rx_data_p, rx_data_n_s}; rx_data_1_2d <= rx_data_1_s;
rx_frame <= {rx_frame_p, rx_frame_n_s}; rx_data_0_2d <= rx_data_0_s;
rx_data_1_d <= rx_data_1;
end
end
// delineation
always @(posedge l_clk) begin
if (rx_valid == 1'b1) begin
case ({rx_r1_mode, rx_frame_s, rx_frame})
5'b01111: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
end
5'b00000: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_1, rx_data_1_s};
adc_data_p[35:24] <= {rx_data_0, rx_data_0_s};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00111: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0, rx_data_0_s};
adc_data_p[11: 0] <= {rx_data_1_2d, rx_data_1};
end
5'b01000: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_0, rx_data_0_s};
adc_data_p[35:24] <= {rx_data_1_2d, rx_data_1};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00011: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1_2d, rx_data_1};
adc_data_p[11: 0] <= {rx_data_0_2d, rx_data_0};
end
5'b01100: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_1_2d, rx_data_1};
adc_data_p[35:24] <= {rx_data_0_2d, rx_data_0};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b00001: begin
adc_valid_p <= 1'b0;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0_2d, rx_data_0};
adc_data_p[11: 0] <= {rx_data_1_d, rx_data_1_2d};
end
5'b01110: begin
adc_valid_p <= 1'b1;
adc_data_p[47:36] <= {rx_data_0_2d, rx_data_0};
adc_data_p[35:24] <= {rx_data_1_d, rx_data_1_2d};
adc_data_p[23: 0] <= adc_data_p[23:0];
end
5'b10011: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
end
5'b11001: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0, rx_data_0_s};
adc_data_p[11: 0] <= {rx_data_1_2d, rx_data_1};
end
5'b11100: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_1_2d, rx_data_1};
adc_data_p[11: 0] <= {rx_data_0_2d, rx_data_0};
end
5'b10110: begin
adc_valid_p <= 1'b1;
adc_data_p[47:24] <= 24'd0;
adc_data_p[23:12] <= {rx_data_0_2d, rx_data_0};
adc_data_p[11: 0] <= {rx_data_1_d, rx_data_1_2d};
end
default: begin
adc_valid_p <= 1'b0;
adc_data_p <= 48'd0;
end
endcase
end else begin end else begin
rx_data <= {rx_data_n_s, rx_data_p_s}; adc_valid_p <= 1'b0;
rx_frame <= {rx_frame_n_s, rx_frame_p_s}; adc_data_p <= adc_data_p;
end end
rx_data_d <= rx_data;
rx_frame_d <= rx_frame;
end end
// receive data path for single rf, frame is expected to qualify i/q msb only // adc-status
always @(posedge l_clk) begin always @(posedge l_clk) begin
rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; if (rx_valid == 1'b1) begin
rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0; if (rx_frame_d == rx_frame_s) begin
if (rx_frame_s == 4'b1100) begin adc_status_p <= rx_locked;
rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
always @(posedge l_clk) begin
rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
if (rx_frame_s == 4'b1111) begin
rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
if (rx_frame_s == 4'b0000) begin
rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path mux
always @(posedge l_clk) begin
if (adc_r1_mode == 1'b1) begin
adc_p_valid <= rx_valid_r1;
adc_p_data <= {24'd0, rx_data_r1};
adc_p_status <= ~rx_error_r1;
end else begin end else begin
adc_p_valid <= rx_valid_r2; adc_status_p <= 1'b0;
adc_p_data <= rx_data_r2; end
adc_p_status <= ~rx_error_r2;
end end
end end
// transfer to a synchronous common clock // transfer to common clock
always @(negedge l_clk) begin always @(negedge l_clk) begin
adc_n_valid <= adc_p_valid; adc_valid_n <= adc_valid_p;
adc_n_data <= adc_p_data; adc_data_n <= adc_data_p;
adc_n_status <= adc_p_status; adc_status_n <= adc_status_p;
end end
assign adc_valid = adc_valid_int;
assign adc_data = adc_data_int;
assign adc_status = adc_status_int;
always @(posedge clk) begin always @(posedge clk) begin
adc_valid_int <= adc_n_valid; adc_valid_int <= adc_valid_n;
adc_data_int <= adc_n_data; adc_data_int <= adc_data_n;
adc_status_int <= adc_n_status; adc_status_int <= adc_status_n;
adc_valid <= adc_valid_int;
if (adc_valid_int == 1'b1) begin
adc_data <= adc_data_int;
end
adc_status <= adc_status_int & locked;
end end
// transmit data path mux (reverse of what receive does above) // dac-tx interface
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
always @(posedge clk) begin always @(posedge clk) begin
if (dac_valid == 1'b1) begin if (dac_valid == 1'b1) begin
tx_data_cnt <= 3'b100; tx_data_sel <= 2'b00;
end else if (tx_data_cnt[2] == 1'b1) begin end else begin
tx_data_cnt <= tx_data_cnt + 1'b1; tx_data_sel <= tx_data_sel + 1'b1;
end end
if (dac_valid == 1'b1) begin if (dac_valid == 1'b1) begin
tx_data <= dac_data; tx_data <= dac_data;
end end
case (tx_data_sel_s)
4'b1111: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data[ 5: 0];
tx_data_n <= tx_data[17:12];
end end
4'b1110: begin
tx_frame <= 1'b1; always @(posedge clk) begin
tx_data_p <= tx_data[11: 6]; tx_clk_p <= {dac_clksel, ~dac_clksel};
tx_data_n <= tx_data[23:18];
end end
4'b1101: begin
tx_frame <= 1'b0; always @(posedge clk) begin
tx_data_p <= tx_data[ 5: 0]; case ({dac_r1_mode, tx_data_sel})
tx_data_n <= tx_data[17:12]; 3'b000: begin
tx_frame_p <= 1'b1;
tx_data_0_p <= tx_data[11:6];
tx_data_1_p <= tx_data[23:18];
end end
4'b1100: begin 3'b001: begin
tx_frame <= 1'b1; tx_frame_p <= 1'b1;
tx_data_p <= tx_data[11: 6]; tx_data_0_p <= tx_data[5:0];
tx_data_n <= tx_data[23:18]; tx_data_1_p <= tx_data[17:12];
end end
4'b1011: begin 3'b010: begin
tx_frame <= 1'b0; tx_frame_p <= 1'b0;
tx_data_p <= tx_data[29:24]; tx_data_0_p <= tx_data[35:30];
tx_data_n <= tx_data[41:36]; tx_data_1_p <= tx_data[47:42];
end end
4'b1010: begin 3'b011: begin
tx_frame <= 1'b0; tx_frame_p <= 1'b0;
tx_data_p <= tx_data[35:30]; tx_data_0_p <= tx_data[29:24];
tx_data_n <= tx_data[47:42]; tx_data_1_p <= tx_data[41:36];
end end
4'b1001: begin 3'b100: begin
tx_frame <= 1'b1; tx_frame_p <= 1'b1;
tx_data_p <= tx_data[ 5: 0]; tx_data_0_p <= tx_data[11:6];
tx_data_n <= tx_data[17:12]; tx_data_1_p <= tx_data[23:18];
end end
4'b1000: begin 3'b101: begin
tx_frame <= 1'b1; tx_frame_p <= 1'b0;
tx_data_p <= tx_data[11: 6]; tx_data_0_p <= tx_data[5:0];
tx_data_n <= tx_data[23:18]; tx_data_1_p <= tx_data[17:12];
end end
default: begin default: begin
tx_frame <= 1'b0; tx_frame_p <= 1'b0;
tx_data_p <= 6'd0; tx_data_0_p <= 6'd0;
tx_data_n <= 6'd0; tx_data_1_p <= 6'd0;
end end
endcase endcase
end end
// transfer data from a synchronous clock (skew less than 2ns) // transfer to local clock
always @(negedge clk) begin always @(negedge clk) begin
tx_n_frame <= tx_frame; tx_clk_n <= tx_clk_p;
tx_n_data_p <= tx_data_p; tx_frame_n <= tx_frame_p;
tx_n_data_n <= tx_data_n; tx_data_0_n <= tx_data_0_p;
tx_data_1_n <= tx_data_1_p;
end end
always @(posedge l_clk) begin always @(posedge l_clk) begin
tx_p_frame <= tx_n_frame; tx_clk <= tx_clk_n;
tx_p_data_p <= tx_n_data_p; tx_frame <= tx_frame_n;
tx_p_data_n <= tx_n_data_n; tx_data_0 <= tx_data_0_n;
tx_data_1 <= tx_data_1_n;
end end
// tdd/ensm control // tdd/ensm control
@ -392,38 +454,34 @@ module axi_ad9361_lvds_if #(
end end
always @(negedge clk) begin always @(negedge clk) begin
enable_n_int <= enable_int; enable_int_n <= enable_int;
txnrx_n_int <= txnrx_int; txnrx_int_n <= txnrx_int;
end end
always @(posedge l_clk) begin always @(posedge l_clk) begin
enable_p_int <= enable_n_int; enable_int_p <= enable_int_n;
txnrx_p_int <= txnrx_n_int; txnrx_int_p <= txnrx_int_n;
end
always @(posedge l_clk) begin
dac_clkdata_p <= dac_clksel;
dac_clkdata_n <= ~dac_clksel;
end end
// receive data interface, ibuf -> idelay -> iddr // receive data interface, ibuf -> idelay -> iddr
genvar i;
generate generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data for (i = 0; i < 6; i = i + 1) begin: g_rx_data
ad_lvds_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data ( i_rx_data (
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_data_in_p[l_inst]), .rx_data_in_p (rx_data_in_p[i]),
.rx_data_in_n (rx_data_in_n[l_inst]), .rx_data_in_n (rx_data_in_n[i]),
.rx_data_p (rx_data_p_s[l_inst]), .rx_data_p (rx_data_1_s[i]),
.rx_data_n (rx_data_n_s[l_inst]), .rx_data_n (rx_data_0_s[i]),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_adc_dld[l_inst]), .up_dld (up_adc_dld[i]),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
@ -432,7 +490,7 @@ module axi_ad9361_lvds_if #(
// receive frame interface, ibuf -> idelay -> iddr // receive frame interface, ibuf -> idelay -> iddr
ad_lvds_in #( ad_data_in #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_CTRL (1), .IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
@ -440,36 +498,35 @@ module axi_ad9361_lvds_if #(
.rx_clk (l_clk), .rx_clk (l_clk),
.rx_data_in_p (rx_frame_in_p), .rx_data_in_p (rx_frame_in_p),
.rx_data_in_n (rx_frame_in_n), .rx_data_in_n (rx_frame_in_n),
.rx_data_p (rx_frame_p_s), .rx_data_p (rx_frame_s[1]),
.rx_data_n (rx_frame_n_s), .rx_data_n (rx_frame_s[0]),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_adc_dld[6]), .up_dld (up_adc_dld[6]),
.up_dwdata (up_adc_dwdata[34:30]), .up_dwdata (up_adc_dwdata[34:30]),
.up_drdata (up_adc_drdata[34:30]), .up_drdata (up_adc_drdata[34:30]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked (delay_locked)); .delay_locked (locked_s));
// transmit data interface, oddr -> obuf // transmit data interface, oddr -> obuf
generate generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data for (i = 0; i < 6; i = i + 1) begin: g_tx_data
ad_lvds_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (0),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_data ( i_tx_data (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_p_data_p[l_inst]), .tx_data_p (tx_data_1[i]),
.tx_data_n (tx_p_data_n[l_inst]), .tx_data_n (tx_data_0[i]),
.tx_data_out_p (tx_data_out_p[l_inst]), .tx_data_out_p (tx_data_out_p[i]),
.tx_data_out_n (tx_data_out_n[l_inst]), .tx_data_out_n (tx_data_out_n[i]),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[l_inst]), .up_dld (up_dac_dld[i]),
.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
.delay_clk (delay_clk), .delay_clk (delay_clk),
.delay_rst (delay_rst), .delay_rst (delay_rst),
.delay_locked ()); .delay_locked ());
@ -478,16 +535,15 @@ module axi_ad9361_lvds_if #(
// transmit frame interface, oddr -> obuf // transmit frame interface, oddr -> obuf
ad_lvds_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (0),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_frame ( i_tx_frame (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (tx_p_frame), .tx_data_p (tx_frame),
.tx_data_n (tx_p_frame), .tx_data_n (tx_frame),
.tx_data_out_p (tx_frame_out_p), .tx_data_out_p (tx_frame_out_p),
.tx_data_out_n (tx_frame_out_n), .tx_data_out_n (tx_frame_out_n),
.up_clk (up_clk), .up_clk (up_clk),
@ -500,16 +556,15 @@ module axi_ad9361_lvds_if #(
// transmit clock interface, oddr -> obuf // transmit clock interface, oddr -> obuf
ad_lvds_out #( ad_data_out #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.SINGLE_ENDED (0),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_tx_clk ( i_tx_clk (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (dac_clkdata_p), .tx_data_p (tx_clk[1]),
.tx_data_n (dac_clkdata_n), .tx_data_n (tx_clk[0]),
.tx_data_out_p (tx_clk_out_p), .tx_data_out_p (tx_clk_out_p),
.tx_data_out_n (tx_clk_out_n), .tx_data_out_n (tx_clk_out_n),
.up_clk (up_clk), .up_clk (up_clk),
@ -522,16 +577,18 @@ module axi_ad9361_lvds_if #(
// enable, oddr -> obuf // enable, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_enable ( i_enable (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (enable_p_int), .tx_data_p (enable_int_p),
.tx_data_n (enable_p_int), .tx_data_n (enable_int_p),
.tx_data_out (enable), .tx_data_out_p (enable),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[8]), .up_dld (up_dac_dld[8]),
.up_dwdata (up_dac_dwdata[44:40]), .up_dwdata (up_dac_dwdata[44:40]),
@ -542,16 +599,18 @@ module axi_ad9361_lvds_if #(
// txnrx, oddr -> obuf // txnrx, oddr -> obuf
ad_cmos_out #( ad_data_out #(
.SINGLE_ENDED (1),
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IODELAY_CTRL (0), .IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP)) .IODELAY_GROUP (IO_DELAY_GROUP))
i_txnrx ( i_txnrx (
.tx_clk (l_clk), .tx_clk (l_clk),
.tx_data_p (txnrx_p_int), .tx_data_p (txnrx_int_p),
.tx_data_n (txnrx_p_int), .tx_data_n (txnrx_int_p),
.tx_data_out (txnrx), .tx_data_out_p (txnrx),
.tx_data_out_n (),
.up_clk (up_clk), .up_clk (up_clk),
.up_dld (up_dac_dld[9]), .up_dld (up_dac_dld[9]),
.up_dwdata (up_dac_dwdata[49:45]), .up_dwdata (up_dac_dwdata[49:45]),
@ -562,16 +621,11 @@ module axi_ad9361_lvds_if #(
// device clock interface (receive clock) // device clock interface (receive clock)
always @(posedge clk) begin ad_data_clk #(
locked_m1 <= locked_s;
locked <= locked_m1;
end
ad_lvds_clk #(
.DEVICE_TYPE (DEVICE_TYPE)) .DEVICE_TYPE (DEVICE_TYPE))
i_clk ( i_clk (
.rst (mmcm_rst), .rst (1'd0),
.locked (locked_s), .locked (),
.clk_in_p (rx_clk_in_p), .clk_in_p (rx_clk_in_p),
.clk_in_n (rx_clk_in_n), .clk_in_n (rx_clk_in_n),
.clk (l_clk)); .clk (l_clk));