axi_spi_engine: Improve constraints

main
Istvan Csomortani 2020-04-20 16:07:53 +01:00 committed by István Csomortáni
parent 3c193296dd
commit ff4ce95110
1 changed files with 4 additions and 6 deletions

View File

@ -12,18 +12,16 @@ set_property ASYNC_REG TRUE \
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
set_false_path -quiet \
-from [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_enable_reg* && IS_SEQUENTIAL}] \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_mem_reset_reg* && IS_SEQUENTIAL}] \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
<: } :>