axi_spi_engine: Improve constraints
parent
3c193296dd
commit
ff4ce95110
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@ -12,18 +12,16 @@ set_property ASYNC_REG TRUE \
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[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
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set_false_path -quiet \
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-from [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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-from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_enable_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_mem_reset_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
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<: } :>
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