diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl
index 17ffbf594..3a3cee0d4 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl
@@ -12,18 +12,16 @@ set_property ASYNC_REG TRUE \
   [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
 
 set_false_path -quiet \
-  -from [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+ -from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
+ -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
 set_false_path -quiet \
-  -from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_enable_reg* && IS_SEQUENTIAL}] \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
 set_false_path -quiet \
   -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
 set_false_path -quiet \
-  -from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_mem_reset_reg* && IS_SEQUENTIAL}] \
-  -to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
 <: } :>