zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer 

Update the file according to HDL guideline.
Replace all occurrences of 2d_transfer with dmac_2d_transfer.
Update axi_dmac/Makefile.
main
Iulia Moldovan 2022-03-31 12:33:10 +01:00 committed by imoldovan
parent d9ec44657f
commit fe713a5e98
8 changed files with 100 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/axi_dmac/Makefile
View File

@ -8,7 +8,6 @@ LIBRARY_NAME := axi_dmac
GENERIC_DEPS += ../common/ad_mem_asym.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += 2d_transfer.v
GENERIC_DEPS += address_generator.v
GENERIC_DEPS += axi_dmac.v
GENERIC_DEPS += axi_dmac_burst_memory.v
@ -24,6 +23,7 @@ GENERIC_DEPS += data_mover.v
GENERIC_DEPS += dest_axi_mm.v
GENERIC_DEPS += dest_axi_stream.v
GENERIC_DEPS += dest_fifo_inf.v
GENERIC_DEPS += dmac_2d_transfer.v
GENERIC_DEPS += inc_id.vh
GENERIC_DEPS += request_arb.v
GENERIC_DEPS += request_generator.v

2
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -37,7 +37,7 @@ ad_ip_files axi_dmac [list \
request_generator.v \
response_handler.v \
axi_register_slice.v \
2d_transfer.v \
dmac_2d_transfer.v \
dest_axi_mm.v \
dest_axi_stream.v \
dest_fifo_inf.v \

2
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -25,7 +25,7 @@ adi_ip_files axi_dmac [list \
"request_generator.v" \
"response_handler.v" \
"axi_register_slice.v" \
"2d_transfer.v" \
"dmac_2d_transfer.v" \
"dest_axi_mm.v" \
"dest_axi_stream.v" \
"dest_fifo_inf.v" \

10
library/axi_dmac/2d_transfer.v → library/axi_dmac/dmac_2d_transfer.v
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -78,9 +78,9 @@ module dmac_2d_transfer #(
input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length,
input out_response_partial,
input out_response_valid,
output reg out_response_ready = 1'b1
output reg out_response_ready = 1'b1);
);
// internal registers
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
@ -95,8 +95,12 @@ reg [1:0] req_id = 'h00;
reg [1:0] eot_id = 'h00;
reg [3:0] last_req = 'h00;
// internal signals
wire out_last;
// signal name changes
assign out_req_dest_address = dest_address;
assign out_req_src_address = src_address;
assign out_req_length = x_length;

2
library/axi_dmac/tb/dma_read_shutdown_tb
View File

@ -3,7 +3,7 @@
SOURCE="$0.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../2d_transfer.v"
SOURCE+=" ../dmac_2d_transfer.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

2
library/axi_dmac/tb/dma_read_tb
View File

@ -2,7 +2,7 @@
SOURCE="dma_read_tb.v"
SOURCE+=" axi_read_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v"

2
library/axi_dmac/tb/dma_write_shutdown_tb
View File

@ -3,7 +3,7 @@
SOURCE="$0.v"
SOURCE+=" axi_write_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../2d_transfer.v"
SOURCE+=" ../dmac_2d_transfer.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"

2
library/axi_dmac/tb/dma_write_tb
View File

@ -2,7 +2,7 @@
SOURCE="dma_write_tb.v"
SOURCE+=" axi_write_slave.v axi_slave.v"
SOURCE+=" ../axi_dmac_transfer.v ../2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v"
SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v"
SOURCE+=" ../axi_dmac_burst_memory.v"
SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v"