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base:constraint: Setting Configuration Bank Voltage Select 

Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
main
Laszlo Nagy 2018-03-02 10:19:36 +00:00 committed by István Csomortáni
parent 758c617c77
commit fe2b43ddd9
4 changed files with 15 additions and 0 deletions
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4
projects/common/ac701/ac701_system_constr.xdc
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@ -67,3 +67,7 @@ set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports iic_rst
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_scl] set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_sda] set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
# setting the vonfiguration bank voltage select
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]

4
projects/common/kc705/kc705_system_constr.xdc
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@ -83,3 +83,7 @@ set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports gpio_bd
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports iic_rstn] set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports iic_rstn]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 DRIVE 8 SLEW SLOW} [get_ports iic_scl] set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 DRIVE 8 SLEW SLOW} [get_ports iic_sda] set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
#Setting the Configuration Bank Voltage Select
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]

3
projects/common/kcu105/kcu105_system_constr.xdc
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@ -52,3 +52,6 @@ set_property -dict {INTERNAL_VREF {0.84}} [get_iobanks 46]
create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p] create_clock -name phy_clk -period 1.60 [get_ports phy_clk_p]
#Setting the Configuration Bank Voltage Select
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]

4
projects/common/vc707/vc707_system_constr.xdc
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@ -69,3 +69,7 @@ set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd
set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn] set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl] set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda] set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
#Setting the Configuration Bank Voltage Select
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]