daq3: A10GX, updated to the ADI JESD204
- changed lane rate to 12.33Gbps - added dac fifomain
Adrian Costina
parent
1b1edd1b03
commit
fe1adb6e4f
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@ -1,13 +1,12 @@
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "1.621 ns" -name rx_ref_clk [get_ports {rx_ref_clk}]
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create_clock -period "1.621 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
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# flash interface
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@ -1,5 +1,10 @@
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set dac_fifo_name avl_ad9152_fifo
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set dac_fifo_address_width 10
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set dac_data_width 128
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set dac_dma_data_width 128
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
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source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl
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source ../common/daq3_qsys.tcl
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@ -130,6 +130,7 @@ module system_top (
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wire spi_miso_s;
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wire spi_mosi_s;
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wire [ 7:0] spi_csn_s;
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wire dac_fifo_bypass;
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wire [ 23:0] flash_addr_raw;
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// daq3
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@ -149,6 +150,7 @@ module system_top (
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// gpio in & out are separate cores
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assign gpio_i[63:40] = gpio_o[63:40];
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assign dac_fifo_bypass = gpio_o[41];
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assign sysref = gpio_o[40];
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assign gpio_i[39:39] = trig;
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@ -221,17 +223,12 @@ module system_top (
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.sys_spi_MOSI (spi_mosi_s),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s),
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.rx_data_0_rx_serial_data (rx_data[0]),
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.rx_data_1_rx_serial_data (rx_data[1]),
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.rx_data_2_rx_serial_data (rx_data[2]),
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.rx_data_3_rx_serial_data (rx_data[3]),
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.rx_serial_data_rx_serial_data (rx_data),
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.rx_ref_clk_clk (rx_ref_clk),
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.rx_sync_export (rx_sync),
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.rx_sysref_export (rx_sysref),
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.tx_data_0_tx_serial_data (tx_data[0]),
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.tx_data_1_tx_serial_data (tx_data[1]),
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.tx_data_2_tx_serial_data (tx_data[2]),
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.tx_data_3_tx_serial_data (tx_data[3]),
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.tx_serial_data_tx_serial_data (tx_data),
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.tx_fifo_bypass_bypass (dac_fifo_bypass),
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.tx_ref_clk_clk (tx_ref_clk),
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.tx_sync_export (tx_sync),
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.tx_sysref_export (tx_sysref),
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@ -1,56 +1,31 @@
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# ad9152-xcvr
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add_instance avl_ad9152_xcvr avl_adxcvr
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set_instance_parameter_value avl_ad9152_xcvr {ID} {0}
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set_instance_parameter_value avl_ad9152_xcvr {TX_OR_RX_N} {1}
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set_instance_parameter_value avl_ad9152_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9152_xcvr {LANE_RATE} {12500.0}
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set_instance_parameter_value avl_ad9152_xcvr {REFCLK_FREQUENCY} {625.0}
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set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_LANES} {4}
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set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_CONVS} {2}
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set_instance_parameter_value avl_ad9152_xcvr {FRM_BCNT} {1}
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set_instance_parameter_value avl_ad9152_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_ad9152_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_ad9152_xcvr {HD} {1}
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set_instance_parameter_value avl_ad9152_xcvr {TX_LANE_MAP} {0 3 1 2}
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add_instance ad9152_jesd204 adi_jesd204
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set_instance_parameter_value ad9152_jesd204 {ID} {0}
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set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1}
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set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3}
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set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665}
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set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} {4}
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set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2}
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add_connection sys_clk.clk avl_ad9152_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_ad9152_xcvr.sys_resetn
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add_connection sys_clk.clk ad9152_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9152_jesd204.sys_resetn
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add_interface tx_ref_clk clock sink
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set_interface_property tx_ref_clk EXPORT_OF avl_ad9152_xcvr.ref_clk
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add_interface tx_data_0 conduit end
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set_interface_property tx_data_0 EXPORT_OF avl_ad9152_xcvr.tx_data_0
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add_interface tx_data_1 conduit end
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set_interface_property tx_data_1 EXPORT_OF avl_ad9152_xcvr.tx_data_1
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add_interface tx_data_2 conduit end
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set_interface_property tx_data_2 EXPORT_OF avl_ad9152_xcvr.tx_data_2
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add_interface tx_data_3 conduit end
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set_interface_property tx_data_3 EXPORT_OF avl_ad9152_xcvr.tx_data_3
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set_interface_property tx_ref_clk EXPORT_OF ad9152_jesd204.ref_clk
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add_interface tx_serial_data conduit end
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set_interface_property tx_serial_data EXPORT_OF ad9152_jesd204.serial_data
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add_interface tx_sysref conduit end
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set_interface_property tx_sysref EXPORT_OF avl_ad9152_xcvr.sysref
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set_interface_property tx_sysref EXPORT_OF ad9152_jesd204.sysref
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add_interface tx_sync conduit end
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set_interface_property tx_sync EXPORT_OF avl_ad9152_xcvr.sync
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# ad9152-xcvr
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add_instance axi_ad9152_xcvr axi_adxcvr
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set_instance_parameter_value axi_ad9152_xcvr {ID} {0}
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set_instance_parameter_value axi_ad9152_xcvr {TX_OR_RX_N} {1}
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set_instance_parameter_value axi_ad9152_xcvr {NUM_OF_LANES} {4}
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add_connection sys_clk.clk axi_ad9152_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9152_xcvr.s_axi_reset
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add_connection axi_ad9152_xcvr.if_up_rst avl_ad9152_xcvr.rst
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add_connection avl_ad9152_xcvr.ready axi_ad9152_xcvr.ready
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add_connection axi_ad9152_xcvr.core_pll_locked avl_ad9152_xcvr.core_pll_locked
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set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync
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# ad9152-core
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add_instance axi_ad9152_core axi_ad9152
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add_connection avl_ad9152_xcvr.core_clk axi_ad9152_core.if_tx_clk
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add_connection axi_ad9152_core.if_tx_data avl_ad9152_xcvr.ip_data
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add_connection ad9152_jesd204.link_clk axi_ad9152_core.if_tx_clk
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add_connection axi_ad9152_core.if_tx_data ad9152_jesd204.link_data
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add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9152_core.s_axi_clock
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@ -60,80 +35,72 @@ add_instance util_ad9152_upack util_upack
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set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64}
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set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2}
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add_connection avl_ad9152_xcvr.core_clk util_ad9152_upack.if_dac_clk
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add_connection ad9152_jesd204.link_clk util_ad9152_upack.if_dac_clk
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add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0
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add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1
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# dac fifo
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add_interface tx_fifo_bypass conduit end
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set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass
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add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk
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add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst
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add_connection util_ad9152_upack.if_dac_valid avl_ad9152_fifo.if_dac_valid
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add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_dac_data
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#add_connection avl_ad9152_fifo.if_dac_dunf util_ad9152_upack.if_dac_dunf
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# ad9152-dma
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add_instance axi_ad9152_dma axi_dmac
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set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128}
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set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {2}
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set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1}
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set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16}
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add_connection avl_ad9152_xcvr.core_clk axi_ad9152_dma.if_fifo_rd_clk
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add_connection util_ad9152_upack.if_dac_valid axi_ad9152_dma.if_fifo_rd_en
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add_connection util_ad9152_upack.if_dac_data axi_ad9152_dma.if_fifo_rd_dout
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add_connection axi_ad9152_dma.if_fifo_rd_underflow axi_ad9152_core.if_dac_dunf
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add_connection sys_clk.clk avl_ad9152_fifo.if_dma_clk
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add_connection sys_clk.clk_reset avl_ad9152_fifo.if_dma_rst
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add_connection sys_clk.clk axi_ad9152_dma.if_m_axis_aclk
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add_connection axi_ad9152_dma.if_m_axis_valid avl_ad9152_fifo.if_dma_valid
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add_connection axi_ad9152_dma.if_m_axis_data avl_ad9152_fifo.if_dma_data
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add_connection axi_ad9152_dma.if_m_axis_last avl_ad9152_fifo.if_dma_xfer_last
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add_connection axi_ad9152_dma.if_m_axis_xfer_req avl_ad9152_fifo.if_dma_xfer_req
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add_connection avl_ad9152_fifo.if_dma_ready axi_ad9152_dma.if_m_axis_ready
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add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset
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add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock
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add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9152_dma.m_src_axi_reset
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9152_dma.m_src_axi_clock
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add_connection sys_clk.clk_reset axi_ad9152_dma.m_src_axi_reset
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add_connection sys_clk.clk axi_ad9152_dma.m_src_axi_clock
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# ad9680-xcvr
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add_instance avl_ad9680_xcvr avl_adxcvr
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set_instance_parameter_value avl_ad9680_xcvr {ID} {1}
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set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2}
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set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {12500.0}
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set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {625.0}
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set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4}
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set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2}
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set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1}
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set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1}
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set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32}
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set_instance_parameter_value avl_ad9680_xcvr {HD} {1}
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add_instance ad9680_jesd204 adi_jesd204
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set_instance_parameter_value ad9680_jesd204 {ID} {1}
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set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0}
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set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {12333.3}
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set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {616.665}
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set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4}
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add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk
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add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn
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add_connection sys_clk.clk ad9680_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk
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add_interface rx_data_0 conduit end
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set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0
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add_interface rx_data_1 conduit end
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set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1
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add_interface rx_data_2 conduit end
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set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2
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add_interface rx_data_3 conduit end
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set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3
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set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk
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add_interface rx_serial_data conduit end
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set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref
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set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync
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# ad9680-xcvr
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add_instance axi_ad9680_xcvr axi_adxcvr
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set_instance_parameter_value axi_ad9680_xcvr {ID} {1}
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set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0}
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set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4}
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add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset
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add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst
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add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready
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add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked
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set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync
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# ad9680
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add_instance axi_ad9680_core axi_ad9680
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add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk
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add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof
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add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data
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add_connection ad9680_jesd204.link_clk axi_ad9680_core.if_rx_clk
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add_connection ad9680_jesd204.link_sof axi_ad9680_core.if_rx_sof
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add_connection ad9680_jesd204.link_data axi_ad9680_core.if_rx_data
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add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
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add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
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@ -144,8 +111,7 @@ set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
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set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
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add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
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add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk
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add_connection ad9680_jesd204.link_clk util_ad9680_cpack.if_adc_clk
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add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
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add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
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@ -157,11 +123,10 @@ set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
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set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
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add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
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add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
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add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk
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add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk
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add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
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add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
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add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
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add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk
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# ad9680-dma
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@ -175,7 +140,7 @@ set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
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add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
|
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add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk
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||||
add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
|
||||
add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data
|
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add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready
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@ -183,56 +148,41 @@ add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
|
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add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
|
||||
add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9680_dma.m_dest_axi_clock
|
||||
|
||||
# reconfig sharing
|
||||
|
||||
add_instance avl_adxcfg_0 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n
|
||||
add_connection avl_adxcfg_0.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_0
|
||||
add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0
|
||||
|
||||
add_instance avl_adxcfg_1 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n
|
||||
add_connection avl_adxcfg_1.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_1
|
||||
add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1
|
||||
|
||||
add_instance avl_adxcfg_2 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n
|
||||
add_connection avl_adxcfg_2.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_2
|
||||
add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2
|
||||
|
||||
add_instance avl_adxcfg_3 avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n
|
||||
add_connection avl_adxcfg_3.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_3
|
||||
add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
add_instance avl_adxcfg_${i} avl_adxcfg
|
||||
add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
|
||||
add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
|
||||
add_connection avl_adxcfg_${i}.rcfg_m0 ad9152_jesd204.phy_reconfig_${i}
|
||||
add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i}
|
||||
}
|
||||
|
||||
# addresses
|
||||
|
||||
ad_cpu_interconnect 0x10404000 avl_adxcfg_0.rcfg_s0
|
||||
ad_cpu_interconnect 0x10504000 avl_adxcfg_0.rcfg_s1
|
||||
ad_cpu_interconnect 0x10405000 avl_adxcfg_1.rcfg_s0
|
||||
ad_cpu_interconnect 0x10505000 avl_adxcfg_1.rcfg_s1
|
||||
ad_cpu_interconnect 0x10406000 avl_adxcfg_2.rcfg_s0
|
||||
ad_cpu_interconnect 0x10506000 avl_adxcfg_2.rcfg_s1
|
||||
ad_cpu_interconnect 0x10407000 avl_adxcfg_3.rcfg_s0
|
||||
ad_cpu_interconnect 0x10507000 avl_adxcfg_3.rcfg_s1
|
||||
ad_cpu_interconnect 0x10400000 avl_ad9152_xcvr.core_pll_reconfig
|
||||
ad_cpu_interconnect 0x10402000 avl_ad9152_xcvr.lane_pll_reconfig
|
||||
ad_cpu_interconnect 0x10401000 avl_ad9152_xcvr.ip_reconfig
|
||||
ad_cpu_interconnect 0x1040c000 axi_ad9152_dma.s_axi
|
||||
ad_cpu_interconnect 0x10410000 axi_ad9152_xcvr.s_axi
|
||||
ad_cpu_interconnect 0x10420000 axi_ad9152_core.s_axi
|
||||
ad_cpu_interconnect 0x10500000 avl_ad9680_xcvr.core_pll_reconfig
|
||||
ad_cpu_interconnect 0x10501000 avl_ad9680_xcvr.ip_reconfig
|
||||
ad_cpu_interconnect 0x1050c000 axi_ad9680_dma.s_axi
|
||||
ad_cpu_interconnect 0x10510000 axi_ad9680_xcvr.s_axi
|
||||
ad_cpu_interconnect 0x10520000 axi_ad9680_core.s_axi
|
||||
ad_cpu_interconnect 0x00400000 ad9152_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00424000 ad9152_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00425000 ad9152_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00426000 ad9152_jesd204.lane_pll_reconfig
|
||||
ad_cpu_interconnect 0x00428000 avl_adxcfg_0.rcfg_s0
|
||||
ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0
|
||||
ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0
|
||||
ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0
|
||||
ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi
|
||||
ad_cpu_interconnect 0x00430000 axi_ad9152_core.s_axi
|
||||
|
||||
ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig
|
||||
ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management
|
||||
ad_cpu_interconnect 0x00445000 ad9680_jesd204.link_pll_reconfig
|
||||
ad_cpu_interconnect 0x00448000 avl_adxcfg_0.rcfg_s1
|
||||
ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1
|
||||
ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1
|
||||
ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1
|
||||
ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi
|
||||
ad_cpu_interconnect 0x00450000 axi_ad9680_core.s_axi
|
||||
|
||||
# dma interconnects
|
||||
|
||||
|
|
@ -241,5 +191,7 @@ ad_dma_interconnect axi_ad9680_dma.m_dest_axi
|
|||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 8 ad9680_jesd204.interrupt
|
||||
ad_cpu_interrupt 9 ad9152_jesd204.interrupt
|
||||
ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender
|
||||
ad_cpu_interrupt 11 axi_ad9152_dma.interrupt_sender
|
||||
|
|
|
|||
Loading…
Reference in New Issue