diff --git a/projects/daq3/a10gx/system_constr.sdc b/projects/daq3/a10gx/system_constr.sdc index 19ad95a2b..7639fc2ed 100644 --- a/projects/daq3/a10gx/system_constr.sdc +++ b/projects/daq3/a10gx/system_constr.sdc @@ -1,13 +1,12 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "1.621 ns" -name rx_ref_clk [get_ports {rx_ref_clk}] +create_clock -period "1.621 ns" -name tx_ref_clk [get_ports {tx_ref_clk}] derive_pll_clocks derive_clock_uncertainty set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] -set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] -set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] # flash interface diff --git a/projects/daq3/a10gx/system_qsys.tcl b/projects/daq3/a10gx/system_qsys.tcl index eaef9df25..46d156494 100644 --- a/projects/daq3/a10gx/system_qsys.tcl +++ b/projects/daq3/a10gx/system_qsys.tcl @@ -1,5 +1,10 @@ +set dac_fifo_name avl_ad9152_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl +source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl source ../common/daq3_qsys.tcl - diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v index bb3e01447..156472a86 100644 --- a/projects/daq3/a10gx/system_top.v +++ b/projects/daq3/a10gx/system_top.v @@ -130,6 +130,7 @@ module system_top ( wire spi_miso_s; wire spi_mosi_s; wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; wire [ 23:0] flash_addr_raw; // daq3 @@ -149,6 +150,7 @@ module system_top ( // gpio in & out are separate cores assign gpio_i[63:40] = gpio_o[63:40]; + assign dac_fifo_bypass = gpio_o[41]; assign sysref = gpio_o[40]; assign gpio_i[39:39] = trig; @@ -221,17 +223,12 @@ module system_top ( .sys_spi_MOSI (spi_mosi_s), .sys_spi_SCLK (spi_clk), .sys_spi_SS_n (spi_csn_s), - .rx_data_0_rx_serial_data (rx_data[0]), - .rx_data_1_rx_serial_data (rx_data[1]), - .rx_data_2_rx_serial_data (rx_data[2]), - .rx_data_3_rx_serial_data (rx_data[3]), + .rx_serial_data_rx_serial_data (rx_data), .rx_ref_clk_clk (rx_ref_clk), .rx_sync_export (rx_sync), .rx_sysref_export (rx_sysref), - .tx_data_0_tx_serial_data (tx_data[0]), - .tx_data_1_tx_serial_data (tx_data[1]), - .tx_data_2_tx_serial_data (tx_data[2]), - .tx_data_3_tx_serial_data (tx_data[3]), + .tx_serial_data_tx_serial_data (tx_data), + .tx_fifo_bypass_bypass (dac_fifo_bypass), .tx_ref_clk_clk (tx_ref_clk), .tx_sync_export (tx_sync), .tx_sysref_export (tx_sysref), diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl index 164b60f14..d0232e346 100644 --- a/projects/daq3/common/daq3_qsys.tcl +++ b/projects/daq3/common/daq3_qsys.tcl @@ -1,56 +1,31 @@ # ad9152-xcvr -add_instance avl_ad9152_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9152_xcvr {ID} {0} -set_instance_parameter_value avl_ad9152_xcvr {TX_OR_RX_N} {1} -set_instance_parameter_value avl_ad9152_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9152_xcvr {LANE_RATE} {12500.0} -set_instance_parameter_value avl_ad9152_xcvr {REFCLK_FREQUENCY} {625.0} -set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_LANES} {4} -set_instance_parameter_value avl_ad9152_xcvr {NUM_OF_CONVS} {2} -set_instance_parameter_value avl_ad9152_xcvr {FRM_BCNT} {1} -set_instance_parameter_value avl_ad9152_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9152_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9152_xcvr {HD} {1} -set_instance_parameter_value avl_ad9152_xcvr {TX_LANE_MAP} {0 3 1 2} +add_instance ad9152_jesd204 adi_jesd204 +set_instance_parameter_value ad9152_jesd204 {ID} {0} +set_instance_parameter_value ad9152_jesd204 {TX_OR_RX_N} {1} +set_instance_parameter_value ad9152_jesd204 {LANE_RATE} {12333.3} +set_instance_parameter_value ad9152_jesd204 {REFCLK_FREQUENCY} {616.665} +set_instance_parameter_value ad9152_jesd204 {NUM_OF_LANES} {4} +set_instance_parameter_value ad9152_jesd204 {LANE_MAP} {0 3 1 2} -add_connection sys_clk.clk avl_ad9152_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9152_xcvr.sys_resetn +add_connection sys_clk.clk ad9152_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9152_jesd204.sys_resetn add_interface tx_ref_clk clock sink -set_interface_property tx_ref_clk EXPORT_OF avl_ad9152_xcvr.ref_clk -add_interface tx_data_0 conduit end -set_interface_property tx_data_0 EXPORT_OF avl_ad9152_xcvr.tx_data_0 -add_interface tx_data_1 conduit end -set_interface_property tx_data_1 EXPORT_OF avl_ad9152_xcvr.tx_data_1 -add_interface tx_data_2 conduit end -set_interface_property tx_data_2 EXPORT_OF avl_ad9152_xcvr.tx_data_2 -add_interface tx_data_3 conduit end -set_interface_property tx_data_3 EXPORT_OF avl_ad9152_xcvr.tx_data_3 +set_interface_property tx_ref_clk EXPORT_OF ad9152_jesd204.ref_clk +add_interface tx_serial_data conduit end +set_interface_property tx_serial_data EXPORT_OF ad9152_jesd204.serial_data add_interface tx_sysref conduit end -set_interface_property tx_sysref EXPORT_OF avl_ad9152_xcvr.sysref +set_interface_property tx_sysref EXPORT_OF ad9152_jesd204.sysref add_interface tx_sync conduit end -set_interface_property tx_sync EXPORT_OF avl_ad9152_xcvr.sync - -# ad9152-xcvr - -add_instance axi_ad9152_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9152_xcvr {ID} {0} -set_instance_parameter_value axi_ad9152_xcvr {TX_OR_RX_N} {1} -set_instance_parameter_value axi_ad9152_xcvr {NUM_OF_LANES} {4} - -add_connection sys_clk.clk axi_ad9152_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9152_xcvr.s_axi_reset -add_connection axi_ad9152_xcvr.if_up_rst avl_ad9152_xcvr.rst -add_connection avl_ad9152_xcvr.ready axi_ad9152_xcvr.ready -add_connection axi_ad9152_xcvr.core_pll_locked avl_ad9152_xcvr.core_pll_locked +set_interface_property tx_sync EXPORT_OF ad9152_jesd204.sync # ad9152-core add_instance axi_ad9152_core axi_ad9152 -add_connection avl_ad9152_xcvr.core_clk axi_ad9152_core.if_tx_clk -add_connection axi_ad9152_core.if_tx_data avl_ad9152_xcvr.ip_data +add_connection ad9152_jesd204.link_clk axi_ad9152_core.if_tx_clk +add_connection axi_ad9152_core.if_tx_data ad9152_jesd204.link_data add_connection sys_clk.clk_reset axi_ad9152_core.s_axi_reset add_connection sys_clk.clk axi_ad9152_core.s_axi_clock @@ -60,80 +35,72 @@ add_instance util_ad9152_upack util_upack set_instance_parameter_value util_ad9152_upack {CHANNEL_DATA_WIDTH} {64} set_instance_parameter_value util_ad9152_upack {NUM_OF_CHANNELS} {2} -add_connection avl_ad9152_xcvr.core_clk util_ad9152_upack.if_dac_clk +add_connection ad9152_jesd204.link_clk util_ad9152_upack.if_dac_clk add_connection axi_ad9152_core.dac_ch_0 util_ad9152_upack.dac_ch_0 add_connection axi_ad9152_core.dac_ch_1 util_ad9152_upack.dac_ch_1 +# dac fifo + +add_interface tx_fifo_bypass conduit end +set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9152_fifo.if_bypass + +add_connection ad9152_jesd204.link_clk avl_ad9152_fifo.if_dac_clk +add_connection ad9152_jesd204.link_reset avl_ad9152_fifo.if_dac_rst +add_connection util_ad9152_upack.if_dac_valid avl_ad9152_fifo.if_dac_valid +add_connection avl_ad9152_fifo.if_dac_data util_ad9152_upack.if_dac_data +#add_connection avl_ad9152_fifo.if_dac_dunf util_ad9152_upack.if_dac_dunf + # ad9152-dma add_instance axi_ad9152_dma axi_dmac set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_SRC} {128} set_instance_parameter_value axi_ad9152_dma {DMA_DATA_WIDTH_DEST} {128} set_instance_parameter_value axi_ad9152_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9152_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_DEST} {1} set_instance_parameter_value axi_ad9152_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_ad9152_dma {FIFO_SIZE} {16} -add_connection avl_ad9152_xcvr.core_clk axi_ad9152_dma.if_fifo_rd_clk -add_connection util_ad9152_upack.if_dac_valid axi_ad9152_dma.if_fifo_rd_en -add_connection util_ad9152_upack.if_dac_data axi_ad9152_dma.if_fifo_rd_dout -add_connection axi_ad9152_dma.if_fifo_rd_underflow axi_ad9152_core.if_dac_dunf +add_connection sys_clk.clk avl_ad9152_fifo.if_dma_clk +add_connection sys_clk.clk_reset avl_ad9152_fifo.if_dma_rst +add_connection sys_clk.clk axi_ad9152_dma.if_m_axis_aclk +add_connection axi_ad9152_dma.if_m_axis_valid avl_ad9152_fifo.if_dma_valid +add_connection axi_ad9152_dma.if_m_axis_data avl_ad9152_fifo.if_dma_data +add_connection axi_ad9152_dma.if_m_axis_last avl_ad9152_fifo.if_dma_xfer_last +add_connection axi_ad9152_dma.if_m_axis_xfer_req avl_ad9152_fifo.if_dma_xfer_req +add_connection avl_ad9152_fifo.if_dma_ready axi_ad9152_dma.if_m_axis_ready add_connection sys_clk.clk_reset axi_ad9152_dma.s_axi_reset add_connection sys_clk.clk axi_ad9152_dma.s_axi_clock -add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9152_dma.m_src_axi_reset -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9152_dma.m_src_axi_clock +add_connection sys_clk.clk_reset axi_ad9152_dma.m_src_axi_reset +add_connection sys_clk.clk axi_ad9152_dma.m_src_axi_clock # ad9680-xcvr -add_instance avl_ad9680_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9680_xcvr {ID} {1} -set_instance_parameter_value avl_ad9680_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value avl_ad9680_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9680_xcvr {LANE_RATE} {12500.0} -set_instance_parameter_value avl_ad9680_xcvr {REFCLK_FREQUENCY} {625.0} -set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_LANES} {4} -set_instance_parameter_value avl_ad9680_xcvr {NUM_OF_CONVS} {2} -set_instance_parameter_value avl_ad9680_xcvr {FRM_BCNT} {1} -set_instance_parameter_value avl_ad9680_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9680_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9680_xcvr {HD} {1} +add_instance ad9680_jesd204 adi_jesd204 +set_instance_parameter_value ad9680_jesd204 {ID} {1} +set_instance_parameter_value ad9680_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9680_jesd204 {LANE_RATE} {12333.3} +set_instance_parameter_value ad9680_jesd204 {REFCLK_FREQUENCY} {616.665} +set_instance_parameter_value ad9680_jesd204 {NUM_OF_LANES} {4} -add_connection sys_clk.clk avl_ad9680_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9680_xcvr.sys_resetn +add_connection sys_clk.clk ad9680_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9680_jesd204.sys_resetn add_interface rx_ref_clk clock sink -set_interface_property rx_ref_clk EXPORT_OF avl_ad9680_xcvr.ref_clk -add_interface rx_data_0 conduit end -set_interface_property rx_data_0 EXPORT_OF avl_ad9680_xcvr.rx_data_0 -add_interface rx_data_1 conduit end -set_interface_property rx_data_1 EXPORT_OF avl_ad9680_xcvr.rx_data_1 -add_interface rx_data_2 conduit end -set_interface_property rx_data_2 EXPORT_OF avl_ad9680_xcvr.rx_data_2 -add_interface rx_data_3 conduit end -set_interface_property rx_data_3 EXPORT_OF avl_ad9680_xcvr.rx_data_3 +set_interface_property rx_ref_clk EXPORT_OF ad9680_jesd204.ref_clk +add_interface rx_serial_data conduit end +set_interface_property rx_serial_data EXPORT_OF ad9680_jesd204.serial_data add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF avl_ad9680_xcvr.sysref +set_interface_property rx_sysref EXPORT_OF ad9680_jesd204.sysref add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF avl_ad9680_xcvr.sync - -# ad9680-xcvr - -add_instance axi_ad9680_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9680_xcvr {ID} {1} -set_instance_parameter_value axi_ad9680_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value axi_ad9680_xcvr {NUM_OF_LANES} {4} - -add_connection sys_clk.clk axi_ad9680_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9680_xcvr.s_axi_reset -add_connection axi_ad9680_xcvr.if_up_rst avl_ad9680_xcvr.rst -add_connection avl_ad9680_xcvr.ready axi_ad9680_xcvr.ready -add_connection axi_ad9680_xcvr.core_pll_locked avl_ad9680_xcvr.core_pll_locked +set_interface_property rx_sync EXPORT_OF ad9680_jesd204.sync # ad9680 add_instance axi_ad9680_core axi_ad9680 -add_connection avl_ad9680_xcvr.core_clk axi_ad9680_core.if_rx_clk -add_connection avl_ad9680_xcvr.ip_sof axi_ad9680_core.if_rx_sof -add_connection avl_ad9680_xcvr.ip_data axi_ad9680_core.if_rx_data +add_connection ad9680_jesd204.link_clk axi_ad9680_core.if_rx_clk +add_connection ad9680_jesd204.link_sof axi_ad9680_core.if_rx_sof +add_connection ad9680_jesd204.link_data axi_ad9680_core.if_rx_data add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset add_connection sys_clk.clk axi_ad9680_core.s_axi_clock @@ -144,8 +111,7 @@ set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64} set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2} add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst -add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst -add_connection avl_ad9680_xcvr.core_clk util_ad9680_cpack.if_adc_clk +add_connection ad9680_jesd204.link_clk util_ad9680_cpack.if_adc_clk add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0 add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1 @@ -157,11 +123,10 @@ set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128} set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16} add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst -add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst -add_connection avl_ad9680_xcvr.core_clk ad9680_adcfifo.if_adc_clk +add_connection ad9680_jesd204.link_clk ad9680_adcfifo.if_adc_clk add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata -add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk +add_connection sys_clk.clk ad9680_adcfifo.if_dma_clk # ad9680-dma @@ -175,7 +140,7 @@ set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0} set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0} set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1} -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk +add_connection sys_clk.clk axi_ad9680_dma.if_s_axis_aclk add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready @@ -183,56 +148,41 @@ add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock -add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset -add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock +add_connection sys_clk.clk_reset axi_ad9680_dma.m_dest_axi_reset +add_connection sys_clk.clk axi_ad9680_dma.m_dest_axi_clock # reconfig sharing -add_instance avl_adxcfg_0 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n -add_connection avl_adxcfg_0.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_0 -add_connection avl_adxcfg_0.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_0 - -add_instance avl_adxcfg_1 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n -add_connection avl_adxcfg_1.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_1 -add_connection avl_adxcfg_1.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_1 - -add_instance avl_adxcfg_2 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n -add_connection avl_adxcfg_2.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_2 -add_connection avl_adxcfg_2.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_2 - -add_instance avl_adxcfg_3 avl_adxcfg -add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk -add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n -add_connection avl_adxcfg_3.rcfg_m0 avl_ad9152_xcvr.phy_reconfig_3 -add_connection avl_adxcfg_3.rcfg_m1 avl_ad9680_xcvr.phy_reconfig_3 +for {set i 0} {$i < 4} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 ad9152_jesd204.phy_reconfig_${i} + add_connection avl_adxcfg_${i}.rcfg_m1 ad9680_jesd204.phy_reconfig_${i} +} # addresses -ad_cpu_interconnect 0x10404000 avl_adxcfg_0.rcfg_s0 -ad_cpu_interconnect 0x10504000 avl_adxcfg_0.rcfg_s1 -ad_cpu_interconnect 0x10405000 avl_adxcfg_1.rcfg_s0 -ad_cpu_interconnect 0x10505000 avl_adxcfg_1.rcfg_s1 -ad_cpu_interconnect 0x10406000 avl_adxcfg_2.rcfg_s0 -ad_cpu_interconnect 0x10506000 avl_adxcfg_2.rcfg_s1 -ad_cpu_interconnect 0x10407000 avl_adxcfg_3.rcfg_s0 -ad_cpu_interconnect 0x10507000 avl_adxcfg_3.rcfg_s1 -ad_cpu_interconnect 0x10400000 avl_ad9152_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x10402000 avl_ad9152_xcvr.lane_pll_reconfig -ad_cpu_interconnect 0x10401000 avl_ad9152_xcvr.ip_reconfig -ad_cpu_interconnect 0x1040c000 axi_ad9152_dma.s_axi -ad_cpu_interconnect 0x10410000 axi_ad9152_xcvr.s_axi -ad_cpu_interconnect 0x10420000 axi_ad9152_core.s_axi -ad_cpu_interconnect 0x10500000 avl_ad9680_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x10501000 avl_ad9680_xcvr.ip_reconfig -ad_cpu_interconnect 0x1050c000 axi_ad9680_dma.s_axi -ad_cpu_interconnect 0x10510000 axi_ad9680_xcvr.s_axi -ad_cpu_interconnect 0x10520000 axi_ad9680_core.s_axi +ad_cpu_interconnect 0x00400000 ad9152_jesd204.link_reconfig +ad_cpu_interconnect 0x00424000 ad9152_jesd204.link_management +ad_cpu_interconnect 0x00425000 ad9152_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00426000 ad9152_jesd204.lane_pll_reconfig +ad_cpu_interconnect 0x00428000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi +ad_cpu_interconnect 0x00430000 axi_ad9152_core.s_axi + +ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig +ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management +ad_cpu_interconnect 0x00445000 ad9680_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00448000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x00449000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x0044a000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x0044b000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x0044c000 axi_ad9680_dma.s_axi +ad_cpu_interconnect 0x00450000 axi_ad9680_core.s_axi # dma interconnects @@ -241,5 +191,7 @@ ad_dma_interconnect axi_ad9680_dma.m_dest_axi # interrupts +ad_cpu_interrupt 8 ad9680_jesd204.interrupt +ad_cpu_interrupt 9 ad9152_jesd204.interrupt ad_cpu_interrupt 10 axi_ad9680_dma.interrupt_sender ad_cpu_interrupt 11 axi_ad9152_dma.interrupt_sender