From fd89458708c199564d40fdb817d249563c69d99f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 19:36:03 +0200 Subject: [PATCH] common: Set cpu interconnect strategy to minimize area There will rarely be concurrent access to the peripheral control bus interconnect, so there is no need to optimize for performace. Setting the interconnect strategy to minimize area can reduce the resource usage by ~90%. Signed-off-by: Lars-Peter Clausen --- projects/common/ac701/ac701_system_bd.tcl | 2 ++ projects/common/kc705/kc705_system_bd.tcl | 2 ++ projects/common/kcu105/kcu105_system_bd.tcl | 2 ++ projects/common/mitx045/mitx045_system_bd.tcl | 1 + projects/common/vc707/vc707_system_bd.tcl | 2 ++ projects/common/zc702/zc702_system_bd.tcl | 1 + projects/common/zc706/zc706_system_bd.tcl | 1 + projects/common/zed/zed_system_bd.tcl | 1 + 8 files changed, 12 insertions(+) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 0029deb9d..3a78831c5 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -95,9 +95,11 @@ set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_ # instance: axi interconnect (lite) set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 9301e0c95..b0fb69f0b 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -108,9 +108,11 @@ set_property -dict [list CONFIG.CONST_VAL {1}] $sys_const_ddr3_1 set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 94eaf1c62..a91d15beb 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -97,9 +97,11 @@ set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_r set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index a2a17dc0d..188bb81e4 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -56,6 +56,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 93843ec47..a141bc0f0 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -98,9 +98,11 @@ set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl # instance: axi interconnect (lite) set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 9ff2f95c8..6b7937c91 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -46,6 +46,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 697c6ad72..d56df9193 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -46,6 +46,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 44ae49eb6..006c9bfa0 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -69,6 +69,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen