scripts: add default memory interconnect
Rejeesh Kutty
parent
fc4e002150
commit
fd66affa42
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@ -16,11 +16,11 @@ variable sys_interrupts_q
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###################################################################################################
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set sys_cpu_interconnect_index 0
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set sys_hp0_interconnect_index 0
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set sys_hp1_interconnect_index 0
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set sys_hp2_interconnect_index 0
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set sys_hp3_interconnect_index 0
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set sys_mem_interconnect_index 0
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set sys_hp0_interconnect_index -1
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set sys_hp1_interconnect_index -1
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set sys_hp2_interconnect_index -1
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set sys_hp3_interconnect_index -1
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set sys_mem_interconnect_index -1
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set sys_interrupts_n 0
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###################################################################################################
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@ -65,14 +65,138 @@ proc ad_connect {p_name_1 p_name_2} {
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###################################################################################################
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###################################################################################################
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proc ad_mem_interconnect {p_sel p_name p_clk} {
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proc ad_mem_interconnect {p_clk p_name} {
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set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets $p_clk]] -regexp "DIR == O"]
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ad_mem_interconnect_int "MEM" $p_clk $p_name
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}
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if {($p_sel == "HP0") && ($sys_zynq == 1)} {
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proc ad_hp0_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP0" $p_clk $p_name
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}
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proc ad_hp1_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP1" $p_clk $p_name
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}
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proc ad_hp2_interconnect {p_clk p_name} {
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ad_mem_interconnect_int "HP2" $p_clk $p_name
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}
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proc ad_hp3_interconnect {p_name p_clk} {
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ad_mem_interconnect_int "HP3" $p_clk $p_name
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}
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###################################################################################################
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###################################################################################################
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proc ad_mem_interconnect_int {p_sel p_clk p_name} {
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global sys_zynq
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global sys_hp0_interconnect_index
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global sys_hp1_interconnect_index
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global sys_hp2_interconnect_index
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global sys_hp3_interconnect_index
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global sys_mem_interconnect_index
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set p_intf_name [lrange [split $p_name "/"] end end]
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set p_cell_name [lrange [split $p_name "/"] 0 0]
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set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_cell_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
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if {$sys_hp0_interconnect_index == 0} {
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}
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}
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if {($p_sel eq "MEM") && ($sys_zynq == 1)} {
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set i_str "S$sys_mem_interconnect_index"
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if {$sys_mem_interconnect_index < 10} {
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set i_str "S0$sys_mem_interconnect_index"
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}
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if {$sys_mem_interconnect_index == -1} {
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ad_connect sys_cpu_resetn axi_mem_interconnect/ARESETN
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ad_connect $p_clk axi_mem_interconnect/ACLK
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ad_connect sys_cpu_resetn axi_mem_interconnect/M00_ARESETN
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ad_connect $p_clk axi_mem_interconnect/M00_ACLK
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ad_connect axi_mem_interconnect/M00_AXI $p_name
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} else {
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ad_connect sys_cpu_resetn axi_mem_interconnect/${i_str}_ARESETN
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ad_connect $p_clk axi_mem_interconnect/${i_str}_ACLK
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ad_connect axi_mem_interconnect/${i_str}_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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}
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set sys_mem_interconnect_index [expr $sys_mem_interconnect_index + 1]
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interconnect {p_address p_name} {
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global sys_zynq
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global sys_addr_cntrl_space
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global sys_cpu_interconnect_index
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set i_str "M$sys_cpu_interconnect_index"
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if {$sys_cpu_interconnect_index < 10} {
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set i_str "M0$sys_cpu_interconnect_index"
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} {
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ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
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ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
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ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
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ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} {
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ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
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ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
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ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
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ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
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}
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set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
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set p_intf [filter [get_bd_intf_pins -of_objects [get_bd_cells $p_name]] \
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-regexp "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"]
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set p_intf_name [lrange [split $p_intf "/"] end end]
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set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
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set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
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ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
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ad_connect sys_cpu_clk ${p_intf_clock}
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ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
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ad_connect sys_cpu_resetn ${p_name}/${p_intf_reset}
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ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_index 0
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foreach p_seg_name $p_seg {
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if {$p_index == 0} {
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set p_seg_range [get_property range $p_seg_name]
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create_bd_addr_seg -range $p_seg_range \
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-offset $p_address $sys_addr_cntrl_space \
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$p_seg_name "SEG_data_${p_name}"
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} else {
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assign_bd_address $p_seg_name
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}
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incr p_index
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}
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}
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###################################################################################################
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@ -130,95 +254,3 @@ proc ad_cpu_interrupt_update {} {
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interconnect {p_address p_name} {
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global sys_zynq
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global sys_addr_cntrl_space
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global sys_cpu_interconnect_index
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set i_str "M$sys_cpu_interconnect_index"
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if {$sys_cpu_interconnect_index < 10} {
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set i_str "M0$sys_cpu_interconnect_index"
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}
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set m_clk_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_clk]] -regexp "DIR == O"]
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set m_reset_source [filter [get_bd_pins -of_objects [get_bd_nets sys_cpu_resetn]] -regexp "DIR == O"]
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} {
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins sys_ps7/M_AXI_GP0_ACLK] \
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[get_bd_pins axi_cpu_interconnect/ACLK] \
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[get_bd_pins axi_cpu_interconnect/S00_ACLK] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins axi_cpu_interconnect/ARESETN] \
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[get_bd_pins axi_cpu_interconnect/S00_ARESETN] \
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$m_reset_source
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connect_bd_intf_net -intf_net sys_ps7_axi \
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[get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \
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[get_bd_intf_pins sys_ps7/M_AXI_GP0]
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} {
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins axi_cpu_interconnect/ACLK] \
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[get_bd_pins axi_cpu_interconnect/S00_ACLK] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins axi_cpu_interconnect/ARESETN] \
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[get_bd_pins axi_cpu_interconnect/S00_ARESETN] \
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$m_reset_source
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connect_bd_intf_net -intf_net sys_mb_axi \
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[get_bd_intf_pins axi_cpu_interconnect/S00_AXI] \
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[get_bd_intf_pins sys_mb/M_AXI_DP]
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}
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set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
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set p_intf [filter [get_bd_intf_pins -of_objects [get_bd_cells $p_name]] \
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-regexp "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"]
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set p_intf_name [lrange [split $p_intf "/"] end end]
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set p_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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set p_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_clock}]]
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set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
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connect_bd_net -net sys_cpu_clk \
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[get_bd_pins "axi_cpu_interconnect/${i_str}_ACLK"] \
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[get_bd_pins ${p_clock}] \
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$m_clk_source
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connect_bd_net -net sys_cpu_resetn \
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[get_bd_pins "axi_cpu_interconnect/${i_str}_ARESETN"] \
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[get_bd_pins ${p_name}/${p_reset}] \
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$m_reset_source
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connect_bd_intf_net -intf_net "${p_name}_axi_lite" \
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[get_bd_intf_pins "axi_cpu_interconnect/${i_str}_AXI"] \
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[get_bd_intf_pins ${p_intf}]
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_index 0
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foreach p_seg_name $p_seg {
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if {$p_index == 0} {
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set p_seg_range [get_property range $p_seg_name]
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create_bd_addr_seg -range $p_seg_range \
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-offset $p_address $sys_addr_cntrl_space \
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$p_seg_name "SEG_data_${p_name}"
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} else {
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assign_bd_address $p_seg_name
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}
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incr p_index
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}
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}
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###################################################################################################
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###################################################################################################
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