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axi_dmac: Fixed type in the altera hardware file

main
Adrian Costina 2015-04-17 14:59:47 +03:00
parent dfc22fc7de
commit fd2f5836f0
1 changed files with 1 additions and 1 deletions
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2
library/axi_dmac/axi_dmac_hw.tcl
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@ -17,7 +17,7 @@ add_fileset_file sync_bits.v VERILOG PATH $ad_hdl_dir/library/commo
add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/common/sync_gray.v add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/common/sync_gray.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file axi_repack.v VERILOG PATH $ad_hdl_dir/library/util_axis_resize/util_axis_resize.v add_fileset_file axi_repack.v VERILOG PATH $ad_hdl_dir/library/util_axis_resize/util_axis_resize.v
add_fileset_file fifo.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/util_axis_fifofifo.v add_fileset_file fifo.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v
add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_gray.v add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_gray.v
add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_gray_pipelined.v add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_gray_pipelined.v
add_fileset_file address_sync.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_sync.v add_fileset_file address_sync.v VERILOG PATH $ad_hdl_dir/library/util_axis_fifo/address_sync.v