common/de10nano: Add de10nano base design
Stanca.Pop
István Csomortáni
parent
6cea8ce777
commit
fd1c3c7cdd
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# de10nano
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# clocks (V11, Y13, E11 - PL 50MHz)
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# clocks (E20, D20 - HPS 25MHz)
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set_location_assignment PIN_V11 -to sys_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk
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# Switches
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set_location_assignment PIN_Y24 -to gpio_bd_i[0]
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set_location_assignment PIN_W24 -to gpio_bd_i[1]
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set_location_assignment PIN_W21 -to gpio_bd_i[2]
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set_location_assignment PIN_W20 -to gpio_bd_i[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[3]
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# LEDs
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set_location_assignment PIN_W15 -to gpio_bd_o[0]
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set_location_assignment PIN_AA24 -to gpio_bd_o[1]
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set_location_assignment PIN_V16 -to gpio_bd_o[2]
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set_location_assignment PIN_V15 -to gpio_bd_o[3]
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set_location_assignment PIN_AF26 -to gpio_bd_o[4]
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set_location_assignment PIN_AE26 -to gpio_bd_o[5]
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set_location_assignment PIN_Y16 -to gpio_bd_o[6]
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set_location_assignment PIN_AA23 -to gpio_bd_o[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[7]
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# push-buttons
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set_location_assignment PIN_AH17 -to gpio_bd_i[4]
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set_location_assignment PIN_AH16 -to gpio_bd_i[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[5]
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# UART
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set_location_assignment PIN_A22 -to uart0_rx
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set_location_assignment PIN_B21 -to uart0_tx
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# SPI interface for ltc2308
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set_location_assignment PIN_V10 -to ltc2308_sclk
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set_location_assignment PIN_AD4 -to ltc2308_miso
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set_location_assignment PIN_AC4 -to ltc2308_mosi
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set_location_assignment PIN_U9 -to ltc2308_cs
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc2308_sclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc2308_miso
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc2308_mosi
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc2308_cs
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# USB
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set_location_assignment PIN_G4 -to usb1_clk
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set_location_assignment PIN_C5 -to usb1_stp
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set_location_assignment PIN_E5 -to usb1_dir
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set_location_assignment PIN_D5 -to usb1_nxt
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set_location_assignment PIN_C10 -to usb1_d[0]
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set_location_assignment PIN_F5 -to usb1_d[1]
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set_location_assignment PIN_C9 -to usb1_d[2]
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set_location_assignment PIN_C4 -to usb1_d[3]
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set_location_assignment PIN_C8 -to usb1_d[4]
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set_location_assignment PIN_D4 -to usb1_d[5]
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set_location_assignment PIN_C7 -to usb1_d[6]
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set_location_assignment PIN_F4 -to usb1_d[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[7]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_clk
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_stp
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_dir
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_nxt
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[0]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[3]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[4]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[5]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[6]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[7]
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set_location_assignment PIN_B8 -to sdio_clk
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set_location_assignment PIN_D14 -to sdio_cmd
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set_location_assignment PIN_C13 -to sdio_d[0]
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set_location_assignment PIN_B6 -to sdio_d[1]
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set_location_assignment PIN_B11 -to sdio_d[2]
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set_location_assignment PIN_B9 -to sdio_d[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_cmd
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[3]
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# ETHERNET
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set_location_assignment PIN_J15 -to eth1_tx_clk
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set_location_assignment PIN_A12 -to eth1_tx_ctl
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set_location_assignment PIN_A16 -to eth1_tx_d[0]
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set_location_assignment PIN_J14 -to eth1_tx_d[1]
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set_location_assignment PIN_A15 -to eth1_tx_d[2]
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set_location_assignment PIN_D17 -to eth1_tx_d[3]
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set_location_assignment PIN_J12 -to eth1_rx_clk
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set_location_assignment PIN_J13 -to eth1_rx_ctl
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set_location_assignment PIN_A14 -to eth1_rx_d[0]
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set_location_assignment PIN_A11 -to eth1_rx_d[1]
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set_location_assignment PIN_C15 -to eth1_rx_d[2]
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set_location_assignment PIN_A9 -to eth1_rx_d[3]
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set_location_assignment PIN_A13 -to eth1_mdc
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set_location_assignment PIN_E16 -to eth1_mdio
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_clk
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_ctl
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[0]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[3]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_clk
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_ctl
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[0]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[3]
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_mdc
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_mdio
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# DDR
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set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_p
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set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_n
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[14]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n
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set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
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set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
|
||||
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_p
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_n
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rzq
|
||||
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_p
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_n
|
||||
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[3]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[4]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[5]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[6]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[7]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[8]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[9]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[10]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[11]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[12]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[13]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[14]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cas_n
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_p
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_n
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cke
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cs_n
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[3]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[3]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[4]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[5]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[6]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[7]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[8]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[9]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[10]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[11]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[12]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[13]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[14]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[15]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[16]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[17]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[18]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[19]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[20]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[21]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[22]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[23]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[24]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[25]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[26]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[27]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[28]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[29]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[30]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[31]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[3]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[0]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[1]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[2]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[3]
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_odt
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ras_n
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_reset_n
|
||||
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
|
||||
|
||||
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
|
||||
|
||||
# DDR3 pin locations
|
||||
|
||||
set_location_assignment PIN_C28 -to ddr3_a[0]
|
||||
set_location_assignment PIN_B28 -to ddr3_a[1]
|
||||
set_location_assignment PIN_E26 -to ddr3_a[2]
|
||||
set_location_assignment PIN_D26 -to ddr3_a[3]
|
||||
set_location_assignment PIN_J21 -to ddr3_a[4]
|
||||
set_location_assignment PIN_J20 -to ddr3_a[5]
|
||||
set_location_assignment PIN_C26 -to ddr3_a[6]
|
||||
set_location_assignment PIN_B26 -to ddr3_a[7]
|
||||
set_location_assignment PIN_F26 -to ddr3_a[8]
|
||||
set_location_assignment PIN_F25 -to ddr3_a[9]
|
||||
set_location_assignment PIN_A24 -to ddr3_a[10]
|
||||
set_location_assignment PIN_B24 -to ddr3_a[11]
|
||||
set_location_assignment PIN_D24 -to ddr3_a[12]
|
||||
set_location_assignment PIN_C24 -to ddr3_a[13]
|
||||
set_location_assignment PIN_G23 -to ddr3_a[14]
|
||||
set_location_assignment PIN_A27 -to ddr3_ba[0]
|
||||
set_location_assignment PIN_H25 -to ddr3_ba[1]
|
||||
set_location_assignment PIN_G25 -to ddr3_ba[2]
|
||||
set_location_assignment PIN_A26 -to ddr3_cas_n
|
||||
set_location_assignment PIN_N21 -to ddr3_ck_p
|
||||
set_location_assignment PIN_N20 -to ddr3_ck_n
|
||||
set_location_assignment PIN_L28 -to ddr3_cke
|
||||
set_location_assignment PIN_L21 -to ddr3_cs_n
|
||||
set_location_assignment PIN_G28 -to ddr3_dm[0]
|
||||
set_location_assignment PIN_P28 -to ddr3_dm[1]
|
||||
set_location_assignment PIN_W28 -to ddr3_dm[2]
|
||||
set_location_assignment PIN_AB28 -to ddr3_dm[3]
|
||||
set_location_assignment PIN_J25 -to ddr3_dq[0]
|
||||
set_location_assignment PIN_J24 -to ddr3_dq[1]
|
||||
set_location_assignment PIN_E28 -to ddr3_dq[2]
|
||||
set_location_assignment PIN_D27 -to ddr3_dq[3]
|
||||
set_location_assignment PIN_J26 -to ddr3_dq[4]
|
||||
set_location_assignment PIN_K26 -to ddr3_dq[5]
|
||||
set_location_assignment PIN_G27 -to ddr3_dq[6]
|
||||
set_location_assignment PIN_F28 -to ddr3_dq[7]
|
||||
set_location_assignment PIN_K25 -to ddr3_dq[8]
|
||||
set_location_assignment PIN_L25 -to ddr3_dq[9]
|
||||
set_location_assignment PIN_J27 -to ddr3_dq[10]
|
||||
set_location_assignment PIN_J28 -to ddr3_dq[11]
|
||||
set_location_assignment PIN_M27 -to ddr3_dq[12]
|
||||
set_location_assignment PIN_M26 -to ddr3_dq[13]
|
||||
set_location_assignment PIN_M28 -to ddr3_dq[14]
|
||||
set_location_assignment PIN_N28 -to ddr3_dq[15]
|
||||
set_location_assignment PIN_N24 -to ddr3_dq[16]
|
||||
set_location_assignment PIN_N25 -to ddr3_dq[17]
|
||||
set_location_assignment PIN_T28 -to ddr3_dq[18]
|
||||
set_location_assignment PIN_U28 -to ddr3_dq[19]
|
||||
set_location_assignment PIN_N26 -to ddr3_dq[20]
|
||||
set_location_assignment PIN_N27 -to ddr3_dq[21]
|
||||
set_location_assignment PIN_R27 -to ddr3_dq[22]
|
||||
set_location_assignment PIN_V27 -to ddr3_dq[23]
|
||||
set_location_assignment PIN_R26 -to ddr3_dq[24]
|
||||
set_location_assignment PIN_R25 -to ddr3_dq[25]
|
||||
set_location_assignment PIN_AA28 -to ddr3_dq[26]
|
||||
set_location_assignment PIN_W26 -to ddr3_dq[27]
|
||||
set_location_assignment PIN_R24 -to ddr3_dq[28]
|
||||
set_location_assignment PIN_T24 -to ddr3_dq[29]
|
||||
set_location_assignment PIN_Y27 -to ddr3_dq[30]
|
||||
set_location_assignment PIN_AA27 -to ddr3_dq[31]
|
||||
set_location_assignment PIN_R17 -to ddr3_dqs_p[0]
|
||||
set_location_assignment PIN_R16 -to ddr3_dqs_n[0]
|
||||
set_location_assignment PIN_R19 -to ddr3_dqs_p[1]
|
||||
set_location_assignment PIN_R18 -to ddr3_dqs_n[1]
|
||||
set_location_assignment PIN_T19 -to ddr3_dqs_p[2]
|
||||
set_location_assignment PIN_T18 -to ddr3_dqs_n[2]
|
||||
set_location_assignment PIN_U19 -to ddr3_dqs_p[3]
|
||||
set_location_assignment PIN_T20 -to ddr3_dqs_n[3]
|
||||
set_location_assignment PIN_D28 -to ddr3_odt
|
||||
set_location_assignment PIN_A25 -to ddr3_ras_n
|
||||
set_location_assignment PIN_V28 -to ddr3_reset_n
|
||||
set_location_assignment PIN_E25 -to ddr3_we_n
|
||||
set_location_assignment PIN_D25 -to ddr3_rzq
|
||||
|
||||
# hdmi
|
||||
|
||||
set_location_assignment PIN_U10 -to hdmi_i2c_scl
|
||||
set_location_assignment PIN_AA4 -to hdmi_i2c_sda
|
||||
set_location_assignment PIN_AG5 -to hdmi_out_clk
|
||||
set_location_assignment PIN_AD12 -to hdmi_data[0]
|
||||
set_location_assignment PIN_AE12 -to hdmi_data[1]
|
||||
set_location_assignment PIN_W8 -to hdmi_data[2]
|
||||
set_location_assignment PIN_Y8 -to hdmi_data[3]
|
||||
set_location_assignment PIN_AD11 -to hdmi_data[4]
|
||||
set_location_assignment PIN_AD10 -to hdmi_data[5]
|
||||
set_location_assignment PIN_AE11 -to hdmi_data[6]
|
||||
set_location_assignment PIN_Y5 -to hdmi_data[7]
|
||||
set_location_assignment PIN_AF10 -to hdmi_data[8]
|
||||
set_location_assignment PIN_Y4 -to hdmi_data[9]
|
||||
set_location_assignment PIN_AE9 -to hdmi_data[10]
|
||||
set_location_assignment PIN_AB4 -to hdmi_data[11]
|
||||
set_location_assignment PIN_AE7 -to hdmi_data[12]
|
||||
set_location_assignment PIN_AF6 -to hdmi_data[13]
|
||||
set_location_assignment PIN_AF8 -to hdmi_data[14]
|
||||
set_location_assignment PIN_AF5 -to hdmi_data[15]
|
||||
set_location_assignment PIN_AE4 -to hdmi_data[16]
|
||||
set_location_assignment PIN_AH2 -to hdmi_data[17]
|
||||
set_location_assignment PIN_AH4 -to hdmi_data[18]
|
||||
set_location_assignment PIN_AH5 -to hdmi_data[19]
|
||||
set_location_assignment PIN_AH6 -to hdmi_data[20]
|
||||
set_location_assignment PIN_AG6 -to hdmi_data[21]
|
||||
set_location_assignment PIN_AF9 -to hdmi_data[22]
|
||||
set_location_assignment PIN_AE8 -to hdmi_data[23]
|
||||
set_location_assignment PIN_AD19 -to hdmi_data_e
|
||||
set_location_assignment PIN_T8 -to hdmi_hsync
|
||||
set_location_assignment PIN_V13 -to hdmi_vsync
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_i2c_scl
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_i2c_sda
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_out_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[16]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[17]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[18]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[19]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[20]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[21]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[22]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[23]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data_e
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_hsync
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_vsync
|
||||
|
||||
# globals
|
||||
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
|
||||
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
# de10nano carrier qsys
|
||||
# system clock
|
||||
|
||||
add_instance sys_clk clock_source
|
||||
set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
|
||||
set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
|
||||
set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
|
||||
add_interface sys_clk clock sink
|
||||
add_interface sys_rst reset sink
|
||||
set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
|
||||
set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
|
||||
|
||||
# hps
|
||||
|
||||
add_instance sys_hps altera_hps
|
||||
set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {F2SDRAM_Type} {AXI-3}
|
||||
set_instance_parameter_value sys_hps {F2SDRAM_Width} {64}
|
||||
set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
|
||||
set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
|
||||
set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
|
||||
set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
|
||||
set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
|
||||
set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
|
||||
set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
|
||||
set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_FREQ} {80.0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {20.0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
|
||||
set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
|
||||
set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
|
||||
set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
|
||||
set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
|
||||
set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
|
||||
set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
|
||||
set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
|
||||
set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
|
||||
set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
|
||||
set_instance_parameter_value sys_hps {MEM_TCL} {7}
|
||||
set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/6}
|
||||
set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/6}
|
||||
set_instance_parameter_value sys_hps {MEM_WTCL} {7}
|
||||
set_instance_parameter_value sys_hps {MEM_RTT_WR} {Dynamic ODT off}
|
||||
set_instance_parameter_value sys_hps {TIMING_TIS} {175}
|
||||
set_instance_parameter_value sys_hps {TIMING_TIH} {250}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDS} {50}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDH} {125}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSQ} {120}
|
||||
set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSCK} {400}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
|
||||
set_instance_parameter_value sys_hps {TIMING_TQSH} {0.38}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
|
||||
set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
|
||||
set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
|
||||
set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
|
||||
set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
|
||||
set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
|
||||
set_instance_parameter_value sys_hps {MEM_TRFC_NS} {300.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TWTR} {4}
|
||||
set_instance_parameter_value sys_hps {MEM_TFAW_NS} {37.5}
|
||||
set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
|
||||
set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.6}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.6}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.02}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
|
||||
add_interface sys_hps_memory conduit end
|
||||
set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
|
||||
add_interface sys_hps_hps_io conduit end
|
||||
set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
|
||||
add_interface sys_hps_h2f_reset reset source
|
||||
set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
|
||||
add_connection sys_clk.clk sys_hps.h2f_axi_clock
|
||||
add_connection sys_clk.clk sys_hps.f2h_axi_clock
|
||||
add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
|
||||
add_interface sys_hps_i2c0 conduit end
|
||||
set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
|
||||
add_interface sys_hps_i2c0_clk clock source
|
||||
set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
|
||||
add_interface sys_hps_i2c0_scl_in clock sink
|
||||
set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
|
||||
|
||||
# cpu/hps handling
|
||||
|
||||
proc ad_cpu_interrupt {m_irq m_port} {
|
||||
|
||||
add_connection sys_hps.f2h_irq0 ${m_port}
|
||||
set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
|
||||
}
|
||||
|
||||
proc ad_cpu_interconnect {m_base m_port} {
|
||||
|
||||
add_connection sys_hps.h2f_lw_axi_master ${m_port}
|
||||
set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
|
||||
}
|
||||
|
||||
proc ad_dma_interconnect {m_port} {
|
||||
|
||||
add_connection ${m_port} sys_hps.f2h_sdram0_data
|
||||
set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram0_data baseAddress {0x0000}
|
||||
|
||||
}
|
||||
|
||||
# common dma interfaces clock
|
||||
|
||||
add_instance sys_dma_clk clock_source
|
||||
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
|
||||
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
|
||||
add_connection sys_dma_clk.clk sys_hps.f2h_sdram0_clock
|
||||
|
||||
# internal memory
|
||||
|
||||
add_instance sys_int_mem altera_avalon_onchip_memory2
|
||||
set_instance_parameter_value sys_int_mem {dualPort} {0}
|
||||
set_instance_parameter_value sys_int_mem {dataWidth} {64}
|
||||
set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
|
||||
set_instance_parameter_value sys_int_mem {initMemContent} {0}
|
||||
add_connection sys_clk.clk sys_int_mem.clk1
|
||||
add_connection sys_clk.clk_reset sys_int_mem.reset1
|
||||
add_connection sys_hps.h2f_axi_master sys_int_mem.s1
|
||||
set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
|
||||
|
||||
# id
|
||||
|
||||
add_instance sys_id altera_avalon_sysid_qsys
|
||||
set_instance_parameter_value sys_id {id} {-1395322110}
|
||||
add_connection sys_clk.clk sys_id.clk
|
||||
add_connection sys_clk.clk_reset sys_id.reset
|
||||
|
||||
# gpio-bd
|
||||
|
||||
add_instance sys_gpio_bd altera_avalon_pio
|
||||
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
|
||||
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_bd {width} {32}
|
||||
add_connection sys_clk.clk sys_gpio_bd.clk
|
||||
add_connection sys_clk.clk_reset sys_gpio_bd.reset
|
||||
add_interface sys_gpio_bd conduit end
|
||||
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
|
||||
|
||||
# gpio-in
|
||||
|
||||
add_instance sys_gpio_in altera_avalon_pio
|
||||
set_instance_parameter_value sys_gpio_in {direction} {Input}
|
||||
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_in {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_in.reset
|
||||
add_connection sys_clk.clk sys_gpio_in.clk
|
||||
add_interface sys_gpio_in conduit end
|
||||
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
||||
|
||||
# gpio-out
|
||||
|
||||
add_instance sys_gpio_out altera_avalon_pio
|
||||
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
||||
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
||||
set_instance_parameter_value sys_gpio_out {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
||||
add_connection sys_clk.clk sys_gpio_out.clk
|
||||
add_interface sys_gpio_out conduit end
|
||||
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
||||
|
||||
# spi
|
||||
|
||||
add_instance sys_spi altera_avalon_spi
|
||||
set_instance_parameter_value sys_spi {clockPhase} {0}
|
||||
set_instance_parameter_value sys_spi {clockPolarity} {1}
|
||||
set_instance_parameter_value sys_spi {dataWidth} {8}
|
||||
set_instance_parameter_value sys_spi {masterSPI} {1}
|
||||
set_instance_parameter_value sys_spi {numberOfSlaves} {1}
|
||||
set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
|
||||
add_connection sys_clk.clk sys_spi.clk
|
||||
add_connection sys_clk.clk_reset sys_spi.reset
|
||||
add_interface sys_spi conduit end
|
||||
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||
|
||||
# spi for LTC2308
|
||||
|
||||
add_instance ltc2308_spi altera_avalon_spi
|
||||
set_instance_parameter_value ltc2308_spi {clockPhase} {0}
|
||||
set_instance_parameter_value ltc2308_spi {clockPolarity} {1}
|
||||
set_instance_parameter_value ltc2308_spi {dataWidth} {8}
|
||||
set_instance_parameter_value ltc2308_spi {masterSPI} {1}
|
||||
set_instance_parameter_value ltc2308_spi {numberOfSlaves} {1}
|
||||
set_instance_parameter_value ltc2308_spi {targetClockRate} {50000000.0}
|
||||
add_connection sys_clk.clk ltc2308_spi.clk
|
||||
add_connection sys_clk.clk_reset ltc2308_spi.reset
|
||||
add_interface ltc2308_spi conduit end
|
||||
set_interface_property ltc2308_spi EXPORT_OF ltc2308_spi.external
|
||||
|
||||
# hdmi
|
||||
|
||||
add_instance axi_hdmi_tx_0 axi_hdmi_tx 1.0
|
||||
set_instance_parameter_value axi_hdmi_tx_0 {CR_CB_N} {0}
|
||||
set_instance_parameter_value axi_hdmi_tx_0 {INTERFACE} {24_BIT}
|
||||
set_instance_parameter_value axi_hdmi_tx_0 {ID} {0}
|
||||
|
||||
add_instance pixel_clk_pll altera_pll
|
||||
set_instance_parameter_value pixel_clk_pll {gui_feedback_clock} {Global Clock}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_operation_mode} {direct}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency0} {74.25}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_phase_shift0} {0}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_phase_shift_deg0} {0.0}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_phout_division} {1}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_pll_auto_reset} {Off}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_pll_bandwidth_preset} {Auto}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_pll_mode} {Fractional-N PLL}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_ps_units0} {ps}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_refclk_switch} {0}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_reference_clock_frequency} {50.0}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_switchover_delay} {0}
|
||||
set_instance_parameter_value pixel_clk_pll {gui_en_reconf} {1}
|
||||
|
||||
add_instance pixel_clk_pll_reconfig altera_pll_reconfig
|
||||
set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
|
||||
set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_MIF} {0}
|
||||
set_instance_parameter_value pixel_clk_pll_reconfig {MIF_FILE_NAME} {}
|
||||
|
||||
add_instance video_dmac axi_dmac
|
||||
set_instance_parameter_value video_dmac {ASYNC_CLK_DEST_REQ_MANUAL} {1}
|
||||
set_instance_parameter_value video_dmac {ASYNC_CLK_REQ_SRC_MANUAL} {1}
|
||||
set_instance_parameter_value video_dmac {ASYNC_CLK_SRC_DEST_MANUAL} {1}
|
||||
set_instance_parameter_value video_dmac {AUTO_ASYNC_CLK} {1}
|
||||
set_instance_parameter_value video_dmac {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value video_dmac {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value video_dmac {CYCLIC} {1}
|
||||
set_instance_parameter_value video_dmac {HAS_AXIS_TLAST} {1}
|
||||
set_instance_parameter_value video_dmac {DMA_2D_TRANSFER} {1}
|
||||
set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_DEST} {64}
|
||||
set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value video_dmac {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value video_dmac {DMA_TYPE_DEST} {1}
|
||||
set_instance_parameter_value video_dmac {DMA_TYPE_SRC} {0}
|
||||
set_instance_parameter_value video_dmac {FIFO_SIZE} {4}
|
||||
set_instance_parameter_value video_dmac {ID} {0}
|
||||
set_instance_parameter_value video_dmac {SYNC_TRANSFER_START} {0}
|
||||
|
||||
add_connection video_dmac.m_axis axi_hdmi_tx_0.vdma_if axi4stream
|
||||
|
||||
add_interface axi_hdmi_tx_0_hdmi_if conduit end
|
||||
set_interface_property axi_hdmi_tx_0_hdmi_if EXPORT_OF axi_hdmi_tx_0.hdmi_if
|
||||
|
||||
add_connection pixel_clk_pll.reconfig_from_pll pixel_clk_pll_reconfig.reconfig_from_pll
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPort {}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPort {}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll width {0}
|
||||
|
||||
add_connection pixel_clk_pll.reconfig_to_pll pixel_clk_pll_reconfig.reconfig_to_pll
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPort {}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPort {}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
|
||||
set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0}
|
||||
|
||||
add_connection sys_clk.clk pixel_clk_pll.refclk
|
||||
add_connection sys_clk.clk_reset pixel_clk_pll.reset
|
||||
|
||||
add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk
|
||||
add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset
|
||||
|
||||
add_connection sys_clk.clk axi_hdmi_tx_0.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_hdmi_tx_0.s_axi_reset
|
||||
|
||||
add_connection sys_clk.clk video_dmac.s_axi_clock
|
||||
add_connection sys_clk.clk_reset video_dmac.s_axi_reset
|
||||
|
||||
add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.hdmi_clock
|
||||
add_connection sys_hps.h2f_user2_clock axi_hdmi_tx_0.vdma_clock
|
||||
add_connection sys_hps.h2f_user2_clock video_dmac.if_m_axis_aclk
|
||||
add_connection sys_hps.h2f_user2_clock video_dmac.m_src_axi_clock
|
||||
add_connection sys_clk.clk_reset video_dmac.m_src_axi_reset
|
||||
|
||||
add_connection video_dmac.m_src_axi sys_hps.f2h_axi_slave
|
||||
set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave arbitrationPriority {1}
|
||||
set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave baseAddress {0x0000}
|
||||
set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave defaultConnection {0}
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 0 sys_gpio_bd.irq
|
||||
ad_cpu_interrupt 1 sys_spi.irq
|
||||
ad_cpu_interrupt 2 sys_gpio_in.irq
|
||||
ad_cpu_interrupt 3 ltc2308_spi.irq
|
||||
ad_cpu_interrupt 7 video_dmac.interrupt_sender
|
||||
|
||||
# cpu interconnects
|
||||
|
||||
ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
|
||||
ad_cpu_interconnect 0x00010000 sys_id.control_slave
|
||||
ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
|
||||
ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
|
||||
ad_cpu_interconnect 0x00080000 video_dmac.s_axi
|
||||
ad_cpu_interconnect 0x00090000 axi_hdmi_tx_0.s_axi
|
||||
ad_cpu_interconnect 0x00100000 pixel_clk_pll_reconfig.mgmt_avalon_slave
|
||||
ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
|
||||
ad_cpu_interconnect 0x0010A000 ltc2308_spi.spi_control_port
|
||||
|
||||
Loading…
Reference in New Issue