From fd0c7f1b1c883be5f6693af88e925e7a954e551c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 15 Jun 2017 10:20:52 -0400 Subject: [PATCH] usdrx1/a10gx- updated to a10gx --- projects/usdrx1/a10gx/system_constr.sdc | 1 + projects/usdrx1/a10gx/system_project.tcl | 111 ++++++++++++--- projects/usdrx1/a10gx/system_qsys.tcl | 2 +- projects/usdrx1/a10gx/system_top.v | 164 +++++++++++++++++++++-- projects/usdrx1/common/usdrx1_qsys.tcl | 67 ++++----- 5 files changed, 269 insertions(+), 76 deletions(-) diff --git a/projects/usdrx1/a10gx/system_constr.sdc b/projects/usdrx1/a10gx/system_constr.sdc index e736947f4..1c0e38bea 100644 --- a/projects/usdrx1/a10gx/system_constr.sdc +++ b/projects/usdrx1/a10gx/system_constr.sdc @@ -4,6 +4,7 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk} derive_pll_clocks derive_clock_uncertainty +set_false_path -to [get_registers *sysref_en_m1*] set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] diff --git a/projects/usdrx1/a10gx/system_project.tcl b/projects/usdrx1/a10gx/system_project.tcl index b757f40b3..f2ddb89de 100644 --- a/projects/usdrx1/a10gx/system_project.tcl +++ b/projects/usdrx1/a10gx/system_project.tcl @@ -2,39 +2,114 @@ source ../../scripts/adi_env.tcl source ../../scripts/adi_project_alt.tcl -adi_project_altera fmcjesdadc1_a10gx +adi_project_altera usdrx1_a10gx source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl # files -set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE ../common/usdrx1_spi.v set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v # lane interface -set_location_assignment PIN_AL8 -to ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P -set_location_assignment PIN_AL7 -to "ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N -set_location_assignment PIN_AW7 -to rx_data[0] ; ## C06 FMCA_DP0_M2C_P -set_location_assignment PIN_AW8 -to "rx_data[0](n)" ; ## C07 FMCA_DP0_M2C_N -set_location_assignment PIN_BA7 -to rx_data[1] ; ## A02 FMCA_DP1_M2C_P -set_location_assignment PIN_BA8 -to "rx_data[1](n)" ; ## A03 FMCA_DP1_M2C_N -set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P -set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N -set_location_assignment PIN_AV5 -to rx_data[3] ; ## A10 FMCA_DP3_M2C_P -set_location_assignment PIN_AV6 -to "rx_data[3](n)" ; ## A11 FMCA_DP3_M2C_N -set_location_assignment PIN_AY17 -to rx_sync ; ## G36 FMCA_HPC_LA33_P -set_location_assignment PIN_AW17 -to rx_sysref ; ## G37 FMCA_HPC_LA33_N -set_location_assignment PIN_BB18 -to spi_csn ; ## G34 FMCA_HPC_LA31_N -set_location_assignment PIN_BB17 -to spi_clk ; ## G33 FMCA_HPC_LA31_P -set_location_assignment PIN_AV20 -to spi_sdio ; ## H37 FMCA_HPC_LA32_P - +set_location_assignment PIN_AL8 -to ref_clk ; ## D04 FMCA_HPC_GBTCLK0_M2C_P +set_location_assignment PIN_AL7 -to "ref_clk(n)" ; ## D05 FMCA_HPC_GBTCLK0_M2C_N +set_location_assignment PIN_AW7 -to rx_data[0] ; ## C06 FMCA_HPC_DP00_M2C_P +set_location_assignment PIN_AW8 -to "rx_data[0](n)" ; ## C07 FMCA_HPC_DP00_M2C_N +set_location_assignment PIN_BA7 -to rx_data[1] ; ## A02 FMCA_HPC_DP01_M2C_P +set_location_assignment PIN_BA8 -to "rx_data[1](n)" ; ## A03 FMCA_HPC_DP01_M2C_N +set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_HPC_DP02_M2C_P +set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_HPC_DP02_M2C_N +set_location_assignment PIN_AV5 -to rx_data[3] ; ## A10 FMCA_HPC_DP03_M2C_P +set_location_assignment PIN_AV6 -to "rx_data[3](n)" ; ## A11 FMCA_HPC_DP03_M2C_N +set_location_assignment PIN_AT5 -to rx_data[4] ; ## A14 FMCA_HPC_DP04_M2C_P +set_location_assignment PIN_AT6 -to "rx_data[4](n)" ; ## A15 FMCA_HPC_DP04_M2C_N +set_location_assignment PIN_AP5 -to rx_data[5] ; ## A18 FMCA_HPC_DP05_M2C_P +set_location_assignment PIN_AP6 -to "rx_data[5](n)" ; ## A19 FMCA_HPC_DP05_M2C_N +set_location_assignment PIN_AN3 -to rx_data[6] ; ## B16 FMCA_HPC_DP06_M2C_P +set_location_assignment PIN_AN4 -to "rx_data[6](n)" ; ## B17 FMCA_HPC_DP06_M2C_N +set_location_assignment PIN_AM5 -to rx_data[7] ; ## B12 FMCA_HPC_DP07_M2C_P +set_location_assignment PIN_AM6 -to "rx_data[7](n)" ; ## B13 FMCA_HPC_DP07_M2C_N set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0] set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1] set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2] set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[4] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[5] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[6] +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[7] + +# sysref & sync + +set_location_assignment PIN_AU18 -to rx_sysref ; ## D23 FMCA_HPC_LA23_P +set_location_assignment PIN_AT18 -to "rx_sysref(n)" ; ## D24 FMCA_HPC_LA23_N +set_location_assignment PIN_AT19 -to rx_sync ; ## D26 FMCA_HPC_LA26_P +set_location_assignment PIN_AT20 -to "rx_sync(n)" ; ## D27 FMCA_HPC_LA26_N +set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync + +# mlo, reset & trigger + +set_location_assignment PIN_AV19 -to afe_mlo ; ## D20 FMCA_HPC_LA17_CC_P +set_location_assignment PIN_AW19 -to "afe_mlo(n)" ; ## D21 FMCA_HPC_LA17_CC_N +set_location_assignment PIN_AY15 -to afe_rst ; ## G27 FMCA_HPC_LA25_P +set_location_assignment PIN_AY14 -to "afe_rst(n)" ; ## G28 FMCA_HPC_LA25_N +set_location_assignment PIN_BB15 -to afe_trig ; ## H28 FMCA_HPC_LA24_P +set_location_assignment PIN_BC15 -to "afe_trig(n)" ; ## H29 FMCA_HPC_LA24_N +set_instance_assignment -name IO_STANDARD LVDS -to afe_mlo +set_instance_assignment -name IO_STANDARD LVDS -to afe_rst +set_instance_assignment -name IO_STANDARD LVDS -to afe_trig + +# spi, gpio & misc +# remove termination resistor on D08 & D09 +# D08 FMCA_HPC_LA01_CC_P PIN_AT10 LVDS fmca_la_rx_clk_p[1] (3C) +# D09 FMCA_HPC_LA01_CC_N PIN_AR11 LVDS fmca_la_rx_clk_n[1] (3C) + +set_location_assignment PIN_AR15 -to spi_fout_enb_clk ; ## C14 FMCA_HPC_LA10_P +set_location_assignment PIN_AT15 -to spi_fout_enb_mlo ; ## C15 FMCA_HPC_LA10_N +set_location_assignment PIN_AW18 -to spi_fout_enb_rst ; ## C18 FMCA_HPC_LA14_P +set_location_assignment PIN_AV18 -to spi_fout_enb_sync ; ## C19 FMCA_HPC_LA14_N +set_location_assignment PIN_AU21 -to spi_fout_enb_sysref ; ## C22 FMCA_HPC_LA18_CC_P +set_location_assignment PIN_AV21 -to spi_fout_enb_trig ; ## C23 FMCA_HPC_LA18_CC_N +set_location_assignment PIN_AV14 -to spi_fout_clk ; ## C10 FMCA_HPC_LA06_P +set_location_assignment PIN_AW14 -to spi_fout_sdio ; ## C11 FMCA_HPC_LA06_N +set_location_assignment PIN_AV11 -to spi_afe_csn[0] ; ## D11 FMCA_HPC_LA05_P +set_location_assignment PIN_AW11 -to spi_afe_csn[1] ; ## D12 FMCA_HPC_LA05_N +set_location_assignment PIN_AW13 -to spi_afe_csn[2] ; ## D14 FMCA_HPC_LA09_P +set_location_assignment PIN_AV13 -to spi_afe_csn[3] ; ## D15 FMCA_HPC_LA09_N +set_location_assignment PIN_AT10 -to spi_afe_clk ; ## D08 FMCA_HPC_LA01_CC_P +set_location_assignment PIN_AR11 -to spi_afe_sdio ; ## D09 FMCA_HPC_LA01_CC_N +set_location_assignment PIN_AR19 -to spi_clk_csn ; ## G10 FMCA_HPC_LA03_N +set_location_assignment PIN_AN19 -to spi_clk_clk ; ## G13 FMCA_HPC_LA08_N +set_location_assignment PIN_AP18 -to spi_clk_sdio ; ## G12 FMCA_HPC_LA08_P +set_location_assignment PIN_AR17 -to afe_pdn ; ## D17 FMCA_HPC_LA13_P +set_location_assignment PIN_AP17 -to afe_stby ; ## D18 FMCA_HPC_LA13_N +set_location_assignment PIN_AP16 -to clk_resetn ; ## G16 FMCA_HPC_LA12_N +set_location_assignment PIN_AR16 -to clk_syncn ; ## G15 FMCA_HPC_LA12_P +set_location_assignment PIN_AT13 -to clk_status ; ## G18 FMCA_HPC_LA16_P +set_location_assignment PIN_AU13 -to amp_disbn ; ## G19 FMCA_HPC_LA16_N +set_location_assignment PIN_AU8 -to prc_sck ; ## G21 FMCA_HPC_LA20_P +set_location_assignment PIN_AT8 -to prc_cnv ; ## G22 FMCA_HPC_LA20_N +set_location_assignment PIN_AW12 -to prc_sdo_i ; ## G24 FMCA_HPC_LA22_P +set_location_assignment PIN_AY12 -to prc_sdo_q ; ## G25 FMCA_HPC_LA22_N +set_location_assignment PIN_AR20 -to dac_sleep ; ## G09 FMCA_HPC_LA03_P +set_location_assignment PIN_AY11 -to dac_data[0] ; ## H26 FMCA_HPC_LA21_N +set_location_assignment PIN_AY10 -to dac_data[1] ; ## H25 FMCA_HPC_LA21_P +set_location_assignment PIN_AU12 -to dac_data[2] ; ## H23 FMCA_HPC_LA19_N +set_location_assignment PIN_AU11 -to dac_data[3] ; ## H22 FMCA_HPC_LA19_P +set_location_assignment PIN_AT9 -to dac_data[4] ; ## H20 FMCA_HPC_LA15_N +set_location_assignment PIN_AR9 -to dac_data[5] ; ## H19 FMCA_HPC_LA15_P +set_location_assignment PIN_AR14 -to dac_data[6] ; ## H17 FMCA_HPC_LA11_N +set_location_assignment PIN_AT14 -to dac_data[7] ; ## H16 FMCA_HPC_LA11_P +set_location_assignment PIN_AU17 -to dac_data[8] ; ## H14 FMCA_HPC_LA07_N +set_location_assignment PIN_AT17 -to dac_data[9] ; ## H13 FMCA_HPC_LA07_P +set_location_assignment PIN_AP19 -to dac_data[10] ; ## H11 FMCA_HPC_LA04_N +set_location_assignment PIN_AN20 -to dac_data[11] ; ## H10 FMCA_HPC_LA04_P +set_location_assignment PIN_AT22 -to dac_data[12] ; ## H08 FMCA_HPC_LA02_N +set_location_assignment PIN_AR22 -to dac_data[13] ; ## H07 FMCA_HPC_LA02_P execute_flow -compile diff --git a/projects/usdrx1/a10gx/system_qsys.tcl b/projects/usdrx1/a10gx/system_qsys.tcl index 6d540c54a..5b950a230 100644 --- a/projects/usdrx1/a10gx/system_qsys.tcl +++ b/projects/usdrx1/a10gx/system_qsys.tcl @@ -1,5 +1,5 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl -source ../common/fmcjesdadc1_qsys.tcl +source ../common/usdrx1_qsys.tcl diff --git a/projects/usdrx1/a10gx/system_top.v b/projects/usdrx1/a10gx/system_top.v index aac06554f..f2b9d9cec 100644 --- a/projects/usdrx1/a10gx/system_top.v +++ b/projects/usdrx1/a10gx/system_top.v @@ -80,21 +80,55 @@ module system_top ( // lane interface input ref_clk, - input rx_sysref, + output rx_sysref, output rx_sync, - input [ 3:0] rx_data, + input [ 7:0] rx_data, - // spi + // mlo, reset & trigger - output spi_csn, - output spi_clk, - inout spi_sdio); + output afe_mlo, + output afe_rst, + output afe_trig, + + // spi, gpio & misc + + output spi_fout_enb_clk, + output spi_fout_enb_mlo, + output spi_fout_enb_rst, + output spi_fout_enb_sync, + output spi_fout_enb_sysref, + output spi_fout_enb_trig, + output spi_fout_clk, + output spi_fout_sdio, + output [ 3:0] spi_afe_csn, + output spi_afe_clk, + inout spi_afe_sdio, + output spi_clk_csn, + output spi_clk_clk, + inout spi_clk_sdio, + output afe_pdn, + output afe_stby, + output clk_resetn, + output clk_syncn, + input clk_status, + output amp_disbn, + output prc_sck, + output prc_cnv, + input prc_sdo_i, + input prc_sdo_q, + output dac_sleep, + output [ 13:0] dac_data); // internal signals wire rx_clk; + wire [ 31:0] rx_ch_wr; + wire [511:0] rx_ch_wdata; + wire rx_ch_wovf; + wire rx_ch_sync; + wire [ 3:0] rx_ch_raddr; wire [ 3:0] rx_ip_sof; - wire [127:0] rx_ip_data; + wire [255:0] rx_ip_data; wire eth_reset; wire eth_mdio_i; wire eth_mdio_o; @@ -103,11 +137,30 @@ module system_top ( wire [ 63:0] gpio_o; wire spi_miso; wire spi_mosi; + wire spi_clk; wire [ 7:0] spi_csn_s; // gpio in & out are separate cores - assign gpio_i[63:32] = gpio_o[63:32]; + assign afe_mlo = 1'b0; + + assign gpio_i[63:57] = gpio_o[63:57]; + assign amp_disbn = gpio_o[56]; + + assign gpio_i[55:40] = gpio_o[55:40]; + assign dac_sleep = gpio_o[54]; + assign dac_data = gpio_o[53:40]; + + assign gpio_i[39:36] = gpio_o[39:36]; + assign afe_stby = gpio_o[39]; + assign afe_pdn = gpio_o[38]; + assign afe_trig = gpio_o[37]; + assign afe_rst = gpio_o[36]; + + assign gpio_i[35:35] = clk_status; + assign gpio_i[34:32] = gpio_o[34:32]; + assign clk_syncn = gpio_o[34]; + assign clk_resetn = gpio_o[33]; // board stuff @@ -118,25 +171,100 @@ module system_top ( assign ddr3_a[14:12] = 3'd0; assign gpio_i[31:27] = gpio_o[31:27]; + assign gpio_i[26:16] = gpio_bd_i; assign gpio_i[15: 0] = gpio_o[15:0]; + assign gpio_bd_o = gpio_o[15:0]; + + // sysref + + ad_sysref_gen i_sysref ( + .core_clk (rx_clk), + .sysref_en (gpio_o[60]), + .sysref_out (rx_sysref)); + + // spi (fanout buffers) + + assign spi_fout_enb_clk = 1'b0; + assign spi_fout_enb_mlo = 1'b0; + assign spi_fout_enb_rst = 1'b0; + assign spi_fout_enb_sync = 1'b0; + assign spi_fout_enb_sysref = 1'b0; + assign spi_fout_enb_trig = 1'b0; + assign spi_fout_clk = 1'b0; + assign spi_fout_sdio = 1'b0; + + // spi (adc) + + assign prc_sck = 1'b0; + assign prc_cnv = 1'b0; + + // spi (main) + + assign spi_afe_csn = spi_csn_s[ 4: 1]; + assign spi_clk_csn = spi_csn_s[ 0: 0]; + assign spi_afe_clk = spi_clk; + assign spi_clk_clk = spi_clk; // instantiations - - assign spi_csn = spi_csn_s[0]; - fmcjesdadc1_spi i_fmcjesdadc1_spi ( - .spi_csn (spi_csn_s[0]), + usdrx1_spi i_spi ( + .spi_afe_csn (spi_csn_s[4:1]), + .spi_clk_csn (spi_csn_s[0]), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); + .spi_afe_sdio (spi_afe_sdio), + .spi_clk_sdio (spi_clk_sdio)); system_bd i_system_bd ( + .rx_ch_wdata_data (rx_ch_wdata), + .rx_ch_wovf_ovf (rx_ch_wovf), + .rx_ch_wr_valid (&rx_ch_wr), + .rx_core_ch_0_enable (), + .rx_core_ch_0_valid (rx_ch_wr[7:0]), + .rx_core_ch_0_data (rx_ch_wdata[127:0]), + .rx_core_ch_1_enable (), + .rx_core_ch_1_valid (rx_ch_wr[15:8]), + .rx_core_ch_1_data (rx_ch_wdata[255:128]), + .rx_core_ch_2_enable (), + .rx_core_ch_2_valid (rx_ch_wr[23:16]), + .rx_core_ch_2_data (rx_ch_wdata[383:256]), + .rx_core_ch_3_enable (), + .rx_core_ch_3_valid (rx_ch_wr[31:24]), + .rx_core_ch_3_data (rx_ch_wdata[511:384]), .rx_core_clk_clk (rx_clk), + .rx_core_ovf_0_ovf (rx_ch_wovf), + .rx_core_ovf_1_ovf (rx_ch_wovf), + .rx_core_ovf_2_ovf (rx_ch_wovf), + .rx_core_ovf_3_ovf (rx_ch_wovf), + .rx_core_sync_0_sync_in (1'b0), + .rx_core_sync_0_sync_out (rx_ch_sync), + .rx_core_sync_0_raddr_in (4'd0), + .rx_core_sync_0_raddr_out (rx_ch_raddr), + .rx_core_sync_1_sync_in (rx_ch_sync), + .rx_core_sync_1_sync_out (), + .rx_core_sync_1_raddr_in (rx_ch_raddr), + .rx_core_sync_1_raddr_out (), + .rx_core_sync_2_sync_in (rx_ch_sync), + .rx_core_sync_2_sync_out (), + .rx_core_sync_2_raddr_in (rx_ch_raddr), + .rx_core_sync_2_raddr_out (), + .rx_core_sync_3_sync_in (rx_ch_sync), + .rx_core_sync_3_sync_out (), + .rx_core_sync_3_raddr_in (rx_ch_raddr), + .rx_core_sync_3_raddr_out (), + .rx_core_unf_0_unf (1'd0), + .rx_core_unf_1_unf (1'd0), + .rx_core_unf_2_unf (1'd0), + .rx_core_unf_3_unf (1'd0), .rx_data_0_rx_serial_data (rx_data[0]), .rx_data_1_rx_serial_data (rx_data[1]), .rx_data_2_rx_serial_data (rx_data[2]), .rx_data_3_rx_serial_data (rx_data[3]), + .rx_data_4_rx_serial_data (rx_data[4]), + .rx_data_5_rx_serial_data (rx_data[5]), + .rx_data_6_rx_serial_data (rx_data[6]), + .rx_data_7_rx_serial_data (rx_data[7]), .rx_ip_data_data (rx_ip_data), .rx_ip_data_valid (), .rx_ip_data_ready (1'b1), @@ -146,9 +274,17 @@ module system_top ( .rx_ip_data_1_data (rx_ip_data[127:64]), .rx_ip_data_1_valid (1'b1), .rx_ip_data_1_ready (), + .rx_ip_data_2_data (rx_ip_data[191:128]), + .rx_ip_data_2_valid (1'b1), + .rx_ip_data_2_ready (), + .rx_ip_data_3_data (rx_ip_data[255:192]), + .rx_ip_data_3_valid (1'b1), + .rx_ip_data_3_ready (), .rx_ip_sof_export (rx_ip_sof), .rx_ip_sof_0_export (rx_ip_sof), .rx_ip_sof_1_export (rx_ip_sof), + .rx_ip_sof_2_export (rx_ip_sof), + .rx_ip_sof_3_export (rx_ip_sof), .rx_ref_clk_clk (ref_clk), .rx_sync_export (rx_sync), .rx_sysref_export (rx_sysref), @@ -184,7 +320,7 @@ module system_top ( .sys_gpio_out_export (gpio_o[63:32]), .sys_rst_reset_n (sys_resetn), .sys_spi_MISO (spi_miso), - .sys_spi_MOSI (spi_mosi_s), + .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), .sys_spi_SS_n (spi_csn_s)); diff --git a/projects/usdrx1/common/usdrx1_qsys.tcl b/projects/usdrx1/common/usdrx1_qsys.tcl index 78d44f95b..d80f5757c 100644 --- a/projects/usdrx1/common/usdrx1_qsys.tcl +++ b/projects/usdrx1/common/usdrx1_qsys.tcl @@ -2,11 +2,10 @@ # usdrx1-xcvr add_instance avl_usdrx1_xcvr avl_adxcvr -set_instance_parameter_value avl_usdrx1_xcvr {ID} {1} +set_instance_parameter_value avl_usdrx1_xcvr {ID} {0} set_instance_parameter_value avl_usdrx1_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG1} +set_instance_parameter_value avl_usdrx1_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} set_instance_parameter_value avl_usdrx1_xcvr {LANE_RATE} {3200.0} -set_instance_parameter_value avl_usdrx1_xcvr {SYSCLK_FREQUENCY} {50.0} set_instance_parameter_value avl_usdrx1_xcvr {PLLCLK_FREQUENCY} {1600.0} set_instance_parameter_value avl_usdrx1_xcvr {REFCLK_FREQUENCY} {80.0} set_instance_parameter_value avl_usdrx1_xcvr {CORECLK_FREQUENCY} {80.0} @@ -49,7 +48,7 @@ set_interface_property rx_ip_data EXPORT_OF avl_usdrx1_xcvr.ip_data # usdrx1-xcvr add_instance axi_usdrx1_xcvr axi_adxcvr -set_instance_parameter_value axi_usdrx1_xcvr {ID} {1} +set_instance_parameter_value axi_usdrx1_xcvr {ID} {0} set_instance_parameter_value axi_usdrx1_xcvr {TX_OR_RX_N} {0} set_instance_parameter_value axi_usdrx1_xcvr {NUM_OF_LANES} {8} @@ -158,14 +157,13 @@ add_connection sys_dma_clk.clk usdrx1_adcfifo.if_dma_clk # usdrx1-dma add_instance axi_usdrx1_dma axi_dmac +set_instance_parameter_value axi_usdrx1_dma {ID} {0} +set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_usdrx1_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_usdrx1_dma {DMA_LENGTH_WIDTH} {24} set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_SRC} {512} set_instance_parameter_value axi_usdrx1_dma {DMA_DATA_WIDTH_DEST} {512} -set_instance_parameter_value axi_usdrx1_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_usdrx1_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_usdrx1_dma {SYNC_TRANSFER_START} {1} -set_instance_parameter_value axi_usdrx1_dma {CYCLIC} {0} -set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_usdrx1_dma {DMA_TYPE_SRC} {1} add_connection sys_dma_clk.clk axi_usdrx1_dma.if_s_axis_aclk add_connection usdrx1_adcfifo.if_dma_wr axi_usdrx1_dma.if_s_axis_valid @@ -184,41 +182,24 @@ add_connection avl_usdrx1_xcvr.core_clk rx_core_clk.in_clk add_interface rx_core_clk clock source set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk -# phy reconfiguration - -add_instance avl_phy_reconfig alt_xcvr_reconfig -set_instance_parameter_value avl_phy_reconfig {number_of_reconfig_interfaces} {8} -set_instance_parameter_value avl_phy_reconfig {gui_split_sizes} {1,1,1,1,1,1,1,1} -add_connection avl_phy_reconfig.ch0_0_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_0 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_0 avl_phy_reconfig.ch0_0_from_xcvr -add_connection avl_phy_reconfig.ch1_1_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_1 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_1 avl_phy_reconfig.ch1_1_from_xcvr -add_connection avl_phy_reconfig.ch2_2_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_2 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_2 avl_phy_reconfig.ch2_2_from_xcvr -add_connection avl_phy_reconfig.ch3_3_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_3 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_3 avl_phy_reconfig.ch3_3_from_xcvr -add_connection avl_phy_reconfig.ch4_4_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_4 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_4 avl_phy_reconfig.ch4_4_from_xcvr -add_connection avl_phy_reconfig.ch5_5_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_5 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_5 avl_phy_reconfig.ch5_5_from_xcvr -add_connection avl_phy_reconfig.ch6_6_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_6 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_6 avl_phy_reconfig.ch6_6_from_xcvr -add_connection avl_phy_reconfig.ch7_7_to_xcvr avl_usdrx1_xcvr.phy_reconfig_to_xcvr_7 -add_connection avl_usdrx1_xcvr.phy_reconfig_from_xcvr_7 avl_phy_reconfig.ch7_7_from_xcvr -add_connection sys_clk.clk_reset avl_phy_reconfig.mgmt_rst_reset -add_connection sys_clk.clk avl_phy_reconfig.mgmt_clk_clk - # addresses -ad_cpu_interconnect 0x00010000 avl_phy_reconfig.reconfig_mgmt -ad_cpu_interconnect 0x00018000 avl_usdrx1_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x00019000 avl_usdrx1_xcvr.ip_reconfig -ad_cpu_interconnect 0x00020000 axi_usdrx1_xcvr.s_axi -ad_cpu_interconnect 0x00050000 axi_ad9671_core_0.s_axi -ad_cpu_interconnect 0x00060000 axi_ad9671_core_1.s_axi -ad_cpu_interconnect 0x00070000 axi_ad9671_core_2.s_axi -ad_cpu_interconnect 0x00080000 axi_ad9671_core_3.s_axi -ad_cpu_interconnect 0x00090000 axi_usdrx1_dma.s_axi +ad_cpu_interconnect 0x00010000 avl_usdrx1_xcvr.phy_reconfig_0 +ad_cpu_interconnect 0x00011000 avl_usdrx1_xcvr.phy_reconfig_1 +ad_cpu_interconnect 0x00012000 avl_usdrx1_xcvr.phy_reconfig_2 +ad_cpu_interconnect 0x00013000 avl_usdrx1_xcvr.phy_reconfig_3 +ad_cpu_interconnect 0x00014000 avl_usdrx1_xcvr.phy_reconfig_4 +ad_cpu_interconnect 0x00015000 avl_usdrx1_xcvr.phy_reconfig_5 +ad_cpu_interconnect 0x00016000 avl_usdrx1_xcvr.phy_reconfig_6 +ad_cpu_interconnect 0x00017000 avl_usdrx1_xcvr.phy_reconfig_7 +ad_cpu_interconnect 0x0001b000 avl_usdrx1_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x0001c000 avl_usdrx1_xcvr.ip_reconfig +ad_cpu_interconnect 0x00030000 axi_usdrx1_xcvr.s_axi +ad_cpu_interconnect 0x00040000 axi_ad9671_core_0.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9671_core_1.s_axi +ad_cpu_interconnect 0x00060000 axi_ad9671_core_2.s_axi +ad_cpu_interconnect 0x00070000 axi_ad9671_core_3.s_axi +ad_cpu_interconnect 0x00080000 axi_usdrx1_dma.s_axi # dma interconnects