diff --git a/projects/ad9213_evb/Makefile b/projects/ad9213_evb/Makefile new file mode 100755 index 000000000..65a31182b --- /dev/null +++ b/projects/ad9213_evb/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2022 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9213_evb/Readme.md b/projects/ad9213_evb/Readme.md new file mode 100755 index 000000000..905a60501 --- /dev/null +++ b/projects/ad9213_evb/Readme.md @@ -0,0 +1,8 @@ +# AD9213 EVB HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/eval-ad9213) + * Parts : [12-Bit, 10.25 GSPS, JESD204B, RF Analog-to-Digital Converter](https://www.analog.com/en/products/ad9213.html) + * Project Doc: ? + * HDL Doc: ? + * Linux Drivers: ? diff --git a/projects/ad9213_evb/common/ad9213_evb_bd.tcl b/projects/ad9213_evb/common/ad9213_evb_bd.tcl new file mode 100755 index 000000000..c221dd2ed --- /dev/null +++ b/projects/ad9213_evb/common/ad9213_evb_bd.tcl @@ -0,0 +1,153 @@ + +# RX parameters for each converter +set RX_NUM_OF_LANES 16 ; # L +set RX_NUM_OF_CONVERTERS 1 ; # M +set RX_SAMPLES_PER_FRAME 1 ; # S +set RX_SAMPLE_WIDTH 16 ; # N/NP + +set RX_SAMPLES_PER_CHANNEL 32 ; # L * 32 / (M * N) + +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl + +set adc_fifo_name axi_ad9213_fifo +set adc_data_width 512 +set adc_dma_data_width 512 + +create_bd_port -dir I glbl_clk_0 + +# adc peripherals + +ad_ip_instance util_adxcvr util_adc_xcvr +ad_ip_parameter util_adc_xcvr CONFIG.CPLL_FBDIV_4_5 5 +ad_ip_parameter util_adc_xcvr CONFIG.TX_NUM_OF_LANES 0 +ad_ip_parameter util_adc_xcvr CONFIG.RX_NUM_OF_LANES 16 +ad_ip_parameter util_adc_xcvr CONFIG.RX_OUT_DIV 1 + +ad_ip_instance axi_adxcvr axi_ad9213_xcvr +ad_ip_parameter axi_ad9213_xcvr CONFIG.ID 0 +ad_ip_parameter axi_ad9213_xcvr CONFIG.NUM_OF_LANES 16 +ad_ip_parameter axi_ad9213_xcvr CONFIG.TX_OR_RX_N 0 +ad_ip_parameter axi_ad9213_xcvr CONFIG.QPLL_ENABLE 1 +ad_ip_parameter axi_ad9213_xcvr CONFIG.LPM_OR_DFE_N 1 +ad_ip_parameter axi_ad9213_xcvr CONFIG.SYS_CLK_SEL 0x3 + +adi_axi_jesd204_rx_create axi_ad9213_jesd 16 +ad_ip_parameter axi_ad9213_jesd/rx CONFIG.SYSREF_IOB false +ad_ip_parameter axi_ad9213_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 + +adi_tpl_jesd204_rx_create rx_ad9213_tpl_core $RX_NUM_OF_LANES \ + $RX_NUM_OF_CONVERTERS \ + $RX_SAMPLES_PER_FRAME \ + $RX_SAMPLE_WIDTH + +ad_ip_instance util_cpack2 util_ad9213_cpack [list \ + NUM_OF_CHANNELS [expr $RX_NUM_OF_CONVERTERS] \ + SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \ +] + +ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width + +ad_ip_instance axi_dmac axi_ad9213_dma +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9213_dma CONFIG.ID 0 +ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad9213_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9213_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_ad9213_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width +ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width + +# reference clocks & resets + +create_bd_port -dir I rx_ref_clk_0 +create_bd_port -dir I rx_ref_clk_1 + +ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/qpll_ref_clk_0 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_4 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_8 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_12 + +ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_0 +ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_1 +ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_2 +ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_3 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_4 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_5 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_6 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_7 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_8 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_9 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_10 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_11 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_12 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_13 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_14 +ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_15 + +ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_qpll_rst_* +ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_cpll_rst_* + +ad_connect $sys_cpu_resetn util_adc_xcvr/up_rstn +ad_connect $sys_cpu_clk util_adc_xcvr/up_clk + +# connections (adc) + +ad_xcvrcon util_adc_xcvr axi_ad9213_xcvr axi_ad9213_jesd {} glbl_clk_0 + +## use global clock as device clock instead of rx_out_clk +delete_bd_objs [get_bd_nets util_adc_xcvr_rx_out_clk_0] + +# connect clocks +# device clock domain +ad_connect glbl_clk_0 rx_ad9213_tpl_core/link_clk + +ad_connect glbl_clk_0 util_ad9213_cpack/clk +ad_connect glbl_clk_0 axi_ad9213_fifo/adc_clk + +# dma clock domain +ad_connect $sys_cpu_clk axi_ad9213_fifo/dma_clk +ad_connect $sys_cpu_clk axi_ad9213_dma/s_axis_aclk + +# connect resets +ad_connect glbl_clk_0_rstgen/peripheral_reset axi_ad9213_fifo/adc_rst +ad_connect glbl_clk_0_rstgen/peripheral_reset util_ad9213_cpack/reset +ad_connect $sys_cpu_resetn axi_ad9213_dma/m_dest_axi_aresetn + +# connect dataflow +ad_connect axi_ad9213_jesd/rx_sof rx_ad9213_tpl_core/link_sof +ad_connect axi_ad9213_jesd/rx_data_tdata rx_ad9213_tpl_core/link_data +ad_connect axi_ad9213_jesd/rx_data_tvalid rx_ad9213_tpl_core/link_valid + +ad_connect rx_ad9213_tpl_core/adc_valid_0 util_ad9213_cpack/fifo_wr_en +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_ad9213_tpl_core/adc_enable_$i util_ad9213_cpack/enable_$i + ad_connect rx_ad9213_tpl_core/adc_data_$i util_ad9213_cpack/fifo_wr_data_$i +} +ad_connect rx_ad9213_tpl_core/adc_dovf util_ad9213_cpack/fifo_wr_overflow + +ad_connect util_ad9213_cpack/packed_fifo_wr_data axi_ad9213_fifo/adc_wdata +ad_connect util_ad9213_cpack/packed_fifo_wr_en axi_ad9213_fifo/adc_wr + +ad_connect axi_ad9213_fifo/dma_wr axi_ad9213_dma/s_axis_valid +ad_connect axi_ad9213_fifo/dma_wdata axi_ad9213_dma/s_axis_data +ad_connect axi_ad9213_fifo/dma_wready axi_ad9213_dma/s_axis_ready +ad_connect axi_ad9213_fifo/dma_xfer_req axi_ad9213_dma/s_axis_xfer_req + +# interconnect (cpu) +ad_cpu_interconnect 0x44a60000 axi_ad9213_xcvr +ad_cpu_interconnect 0x44a10000 rx_ad9213_tpl_core +ad_cpu_interconnect 0x44a90000 axi_ad9213_jesd +ad_cpu_interconnect 0x7c420000 axi_ad9213_dma + +# interconnect (gt/adc) +ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_xcvr/m_axi +ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_dma/m_dest_axi + +# interrupts +ad_cpu_interrupt ps-12 mb-12 axi_ad9213_dma/irq +ad_cpu_interrupt ps-11 mb-13 axi_ad9213_jesd/irq diff --git a/projects/ad9213_evb/vcu118/Makefile b/projects/ad9213_evb/vcu118/Makefile new file mode 100755 index 000000000..e9e434674 --- /dev/null +++ b/projects/ad9213_evb/vcu118/Makefile @@ -0,0 +1,28 @@ +#################################################################################### +## Copyright (c) 2018 - 2022 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9213_evb_vcu118 + +M_DEPS += ../common/ad9213_evb_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc +M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9213_evb/vcu118/system_bd.tcl b/projects/ad9213_evb/vcu118/system_bd.tcl new file mode 100755 index 000000000..fa2827476 --- /dev/null +++ b/projects/ad9213_evb/vcu118/system_bd.tcl @@ -0,0 +1,33 @@ + +## FIFO depth is 4Mb - 250k samples (65k samples per converter) +set adc_fifo_address_width 13 + +source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source ../common/ad9213_evb_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +# Set SPI clock to 100/16 = 6.25 MHz +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 16 + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +ad_ip_parameter util_adc_xcvr CONFIG.RX_CLK25_DIV 30 +ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG1 0x2b +ad_ip_parameter util_adc_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_adc_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_adc_xcvr CONFIG.CH_HSPMUX 0x4040 +ad_ip_parameter util_adc_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_adc_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 +ad_ip_parameter util_adc_xcvr CONFIG.RXPI_CFG0 0x3002 +ad_ip_parameter util_adc_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_adc_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_adc_xcvr CONFIG.QPLL_CFG4 0x2 +ad_ip_parameter util_adc_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_adc_xcvr CONFIG.PPF0_CFG 0xB00 diff --git a/projects/ad9213_evb/vcu118/system_constr.xdc b/projects/ad9213_evb/vcu118/system_constr.xdc new file mode 100755 index 000000000..5b21b1229 --- /dev/null +++ b/projects/ad9213_evb/vcu118/system_constr.xdc @@ -0,0 +1,89 @@ +# +## ad9213_evb +# + +# +## FMCp_PORT FPGA_IO +# +set_property -dict {PACKAGE_PIN AN45} [get_ports rx_data_p[3]] ; ## DP1_M2C_P MGTYRXP1_121 +set_property -dict {PACKAGE_PIN AN46} [get_ports rx_data_n[3]] ; ## DP1_M2C_N MGTYRXN1_121 +set_property -dict {PACKAGE_PIN AL45} [get_ports rx_data_p[2]] ; ## DP2_M2C_P MGTYRXP2_121 +set_property -dict {PACKAGE_PIN AL46} [get_ports rx_data_n[2]] ; ## DP2_M2C_N MGTYRXN2_121 +set_property -dict {PACKAGE_PIN AJ45} [get_ports rx_data_p[4]] ; ## DP3_M2C_P MGTYRXP3_121 +set_property -dict {PACKAGE_PIN AJ46} [get_ports rx_data_n[4]] ; ## DP3_M2C_N MGTYRXN3_121 +set_property -dict {PACKAGE_PIN W45} [get_ports rx_data_p[0]] ; ## DP4_M2C_P MGTYRXP0_126 +set_property -dict {PACKAGE_PIN W46} [get_ports rx_data_n[0]] ; ## DP4_M2C_N MGTYRXN0_126 +set_property -dict {PACKAGE_PIN U45} [get_ports rx_data_p[15]] ; ## DP5_M2C_P MGTYRXP1_126 +set_property -dict {PACKAGE_PIN U46} [get_ports rx_data_n[15]] ; ## DP5_M2C_N MGTYRXN1_126 +set_property -dict {PACKAGE_PIN N45} [get_ports rx_data_p[7]] ; ## DP7_M2C_P MGTYRXP3_126 +set_property -dict {PACKAGE_PIN N46} [get_ports rx_data_n[7]] ; ## DP7_M2C_N MGTYRXN3_126 +set_property -dict {PACKAGE_PIN R45} [get_ports rx_data_p[8]] ; ## DP6_M2C_P MGTYRXP2_126 +set_property -dict {PACKAGE_PIN R46} [get_ports rx_data_n[8]] ; ## DP6_M2C_N MGTYRXN2_126 +set_property -dict {PACKAGE_PIN AR45} [get_ports rx_data_p[1]] ; ## DP0_M2C_P MGTYRXP0_121 +set_property -dict {PACKAGE_PIN AR46} [get_ports rx_data_n[1]] ; ## DP0_M2C_N MGTYRXN0_121 +set_property -dict {PACKAGE_PIN AC45} [get_ports rx_data_p[5]] ; ## DP12_M2C_P MGTYRXP0_125 +set_property -dict {PACKAGE_PIN AC46} [get_ports rx_data_n[5]] ; ## DP12_M2C_N MGTYRXN0_125 +set_property -dict {PACKAGE_PIN AA45} [get_ports rx_data_p[10]] ; ## DP14_M2C_P MGTYRXP2_125 +set_property -dict {PACKAGE_PIN AA46} [get_ports rx_data_n[10]] ; ## DP14_M2C_N MGTYRXN2_125 +set_property -dict {PACKAGE_PIN Y43} [get_ports rx_data_p[9]] ; ## DP15_M2C_P MGTYRXP3_125 +set_property -dict {PACKAGE_PIN Y44} [get_ports rx_data_n[9]] ; ## DP15_M2C_N MGTYRXN3_125 +set_property -dict {PACKAGE_PIN J45} [get_ports rx_data_p[14]] ; ## DP17_M2C_P MGTYRXP1_127 +set_property -dict {PACKAGE_PIN J46} [get_ports rx_data_n[14]] ; ## DP17_M2C_N MGTYRXN1_127 +set_property -dict {PACKAGE_PIN E45} [get_ports rx_data_p[11]] ; ## DP19_M2C_P MGTYRXP3_127 +set_property -dict {PACKAGE_PIN E46} [get_ports rx_data_n[11]] ; ## DP19_M2C_N MGTYRXN3_127 +set_property -dict {PACKAGE_PIN AB43} [get_ports rx_data_p[6]] ; ## DP13_M2C_P MGTYRXP1_125 +set_property -dict {PACKAGE_PIN AB44} [get_ports rx_data_n[6]] ; ## DP13_M2C_N MGTYRXN1_125 +set_property -dict {PACKAGE_PIN L45} [get_ports rx_data_p[12]] ; ## DP16_M2C_P MGTYRXP0_127 +set_property -dict {PACKAGE_PIN L46} [get_ports rx_data_n[12]] ; ## DP16_M2C_N MGTYRXN0_127 +set_property -dict {PACKAGE_PIN G45} [get_ports rx_data_p[13]] ; ## DP18_M2C_P MGTYRXP2_127 +set_property -dict {PACKAGE_PIN G46} [get_ports rx_data_n[13]] ; ## DP18_M2C_N MGTYRXN2_127 + +set_property -dict {PACKAGE_PIN AK38} [get_ports rx_ref_clk_p] ; ## GBTCLK0_M2C_P MGTREFCLK0P_121 +set_property -dict {PACKAGE_PIN AK39} [get_ports rx_ref_clk_n] ; ## GBTCLK0_M2C_N MGTREFCLK0N_121 +set_property -dict {PACKAGE_PIN V38} [get_ports rx_ref_clk_replica_p] ; ## GBTCLK0_M2C_P MGTREFCLK0P_126 +set_property -dict {PACKAGE_PIN V39} [get_ports rx_ref_clk_replica_n] ; ## GBTCLK0_M2C_N MGTREFCLK0N_126 + +set_property -dict {PACKAGE_PIN AB38} [get_ports glbl_clk_0_p] ; ## GBTCLK3_M2C_P MGTREFCLK0P_125 +set_property -dict {PACKAGE_PIN AB39} [get_ports glbl_clk_0_n] ; ## GBTCLK3_M2C_N MGTREFCLK0N_125 + +set_property -dict {PACKAGE_PIN AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## LA02_P IO_L14P_T2L_N2_GC_43 +set_property -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## LA02_N IO_L14N_T2L_N3_GC_43 + +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## LA04_P IO_L6P_T0U_N10_AD6P_43 +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## LA04_N IO_L6N_T0U_N11_AD6N_43 + +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18} [get_ports fpga_sdio] ; ## LA06_P IO_L2P_T0L_N2_43 +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD LVCMOS18} [get_ports fpga_sclk] ; ## LA06_N IO_L2N_T0L_N3_43 +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD LVCMOS18} [get_ports fpga_csb] ; ## LA07_P IO_L5P_T0U_N8_AD14P_43 +set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18} [get_ports hmc7044_sdio] ; ## LA15_P IO_L24P_T3U_N10_43 +set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVCMOS18} [get_ports hmc7044_csb] ; ## LA14_P IO_L23P_T3U_N8_43 +set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVCMOS18} [get_ports hmc7044_sclk] ; ## LA14_N IO_L23N_T3U_N9_43 +set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVCMOS18} [get_ports adf4371_sclk] ; ## LA16_P IO_L22P_T3U_N6_DBC_AD0P_43 +set_property -dict {PACKAGE_PIN AH35 IOSTANDARD LVCMOS18} [get_ports adf4371_sdio] ; ## LA16_N IO_L22N_T3U_N7_DBC_AD0N_43 +set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVCMOS18} [get_ports adf4371_csb] ; ## LA19_P IO_L22P_T3U_N6_DBC_AD0P_45 +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS18} [get_ports gpio[0]] ; ## LA08_P IO_L18P_T2U_N10_AD2P_43 +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS18} [get_ports gpio[1]] ; ## LA08_N IO_L18N_T2U_N11_AD2N_43 +set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports gpio[2]] ; ## LA09_P IO_L19P_T3L_N0_DBC_AD9P_43 +set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18} [get_ports gpio[3]] ; ## LA09_N IO_L19N_T3L_N1_DBC_AD9N_43 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD LVCMOS18} [get_ports gpio[4]] ; ## LA10_P IO_L3P_T0L_N4_AD15P_43 +set_property -dict {PACKAGE_PIN AJ35 IOSTANDARD LVCMOS18} [get_ports rstb] ; ## LA13_P IO_L20P_T3L_N2_AD1P_43 +set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVCMOS18} [get_ports hmc_sync_req] ; ## LA13_N IO_L20N_T3L_N3_AD1N_43 + + +# Primary clock definitions + +# These two reference clocks are connect to the same source on the PCB +create_clock -name rx_ref_clk -period 1.33 [get_ports rx_ref_clk_p] +create_clock -name rx_ref_clk_replica -period 1.33 [get_ports rx_ref_clk_replica_p] + +# The Global clock is routed from the REFCLK1 of the dual_ad9208 board +# since GLBLCLK0 and GLBLCLK1 are not connected to global clock capable pins. +create_clock -name global_clk_0 -period 2.66 [get_ports glbl_clk_0_p] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Center-Aligned signal to REFCLK +set_input_delay -clock [get_clocks global_clk_0] \ + [expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \ + [get_ports {rx_sysref_*}] + diff --git a/projects/ad9213_evb/vcu118/system_project.tcl b/projects/ad9213_evb/vcu118/system_project.tcl new file mode 100755 index 000000000..5a5a3f4b6 --- /dev/null +++ b/projects/ad9213_evb/vcu118/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad9213_evb_vcu118 +adi_project_files ad9213_evb_vcu118 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] + +## To improve timing in DDR4 MIG +set_property strategy Performance_SpreadSLLs [get_runs impl_1] + +adi_project_run ad9213_evb_vcu118 + diff --git a/projects/ad9213_evb/vcu118/system_top.v b/projects/ad9213_evb/vcu118/system_top.v new file mode 100755 index 000000000..f680228e4 --- /dev/null +++ b/projects/ad9213_evb/vcu118/system_top.v @@ -0,0 +1,300 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + // FMC+ IOs + + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_ref_clk_replica_p, + input rx_ref_clk_replica_n, + input [15:0] rx_data_p, + input [15:0] rx_data_n, + + input glbl_clk_0_p, + input glbl_clk_0_n, + + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + + output fpga_sclk, + inout fpga_sdio, + output fpga_csb, + + output hmc7044_sclk, + inout hmc7044_sdio, + output hmc7044_csb, + + output adf4371_sclk, + inout adf4371_sdio, + output adf4371_csb, + + inout [ 4:0] gpio, + + output rstb, + output hmc_sync_req +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire spi_clk; + wire [ 7:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire spi_sdio; + + wire rx_ref_clk; + wire rx_ref_clk_replica; + wire rx_sysref; + wire rx_sync; + + assign iic_rstn = 1'b1; + + // spi + + assign fpga_csb = spi_csn[0]; + assign fpga_sclk = spi_clk; + assign fpga_sdio = spi_sdio; + + assign hmc7044_csb = spi_csn[1]; + assign hmc7044_sclk = spi_clk; + assign hmc7044_sdio = spi_sdio; + + assign adf4371_csb = spi_csn[2]; + assign adf4371_sclk = spi_clk; + assign adf4371_sdio = spi_sdio; + + // instantiations + + IBUFDS_GTE4 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_rx_ref_clk_replica ( + .CEB (1'd0), + .I (rx_ref_clk_replica_p), + .IB (rx_ref_clk_replica_n), + .O (rx_ref_clk_replica), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) + ) i_ibufds_glbl_clk_0 ( + .I (glbl_clk_0_p), + .IB (glbl_clk_0_n), + .ODIV2 (glbl_clk_0)); + + BUFG_GT i_bufg( + .I (glbl_clk_0), + .O (glbl_clk_buf)); + + ad_3w_spi #( + .NUM_OF_SLAVES(3) + ) i_spi ( + .spi_csn(spi_csn[3:0]), + .spi_clk(spi_clk), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), + .spi_sdio(spi_sdio), + .spi_dir()); + + ad_iobuf #( + .DATA_WIDTH(5) + ) i_iobuf ( + .dio_t (gpio_t[36:32]), + .dio_i (gpio_o[36:32]), + .dio_o (gpio_i[36:32]), + .dio_p ({gpio[4:0]})); // 36-32 + + assign hmc_sync_req = gpio_o[37]; + assign rstb = gpio_o[38]; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign gpio_i[63:38] = gpio_o[63:38]; + assign gpio_i[31:17] = gpio_o[31:17]; + + system_wrapper i_system_wrapper ( + .sys_rst (sys_rst), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .ddr4_act_n (ddr4_act_n), + .ddr4_adr (ddr4_addr), + .ddr4_ba (ddr4_ba), + .ddr4_bg (ddr4_bg), + .ddr4_ck_c (ddr4_ck_n), + .ddr4_ck_t (ddr4_ck_p), + .ddr4_cke (ddr4_cke), + .ddr4_cs_n (ddr4_cs_n), + .ddr4_dm_n (ddr4_dm_n), + .ddr4_dq (ddr4_dq), + .ddr4_dqs_c (ddr4_dqs_n), + .ddr4_dqs_t (ddr4_dqs_p), + .ddr4_odt (ddr4_odt), + .ddr4_reset_n (ddr4_reset_n), + .phy_sd (1'b1), + .phy_rst_n (phy_rst_n), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .sgmii_phyclk_clk_n (phy_clk_n), + .sgmii_phyclk_clk_p (phy_clk_p), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + // FMC+ + .rx_data_0_n (rx_data_n[1]), + .rx_data_0_p (rx_data_p[1]), + .rx_data_1_n (rx_data_n[2]), + .rx_data_1_p (rx_data_p[2]), + .rx_data_2_n (rx_data_n[3]), + .rx_data_2_p (rx_data_p[3]), + .rx_data_3_n (rx_data_n[4]), + .rx_data_3_p (rx_data_p[4]), + .rx_data_4_n (rx_data_n[0]), + .rx_data_4_p (rx_data_p[0]), + .rx_data_5_n (rx_data_n[15]), + .rx_data_5_p (rx_data_p[15]), + .rx_data_6_n (rx_data_n[7]), + .rx_data_6_p (rx_data_p[7]), + .rx_data_7_n (rx_data_n[8]), + .rx_data_7_p (rx_data_p[8]), + .rx_data_8_n (rx_data_n[5]), + .rx_data_8_p (rx_data_p[5]), + .rx_data_9_n (rx_data_n[10]), + .rx_data_9_p (rx_data_p[10]), + .rx_data_10_n (rx_data_n[9]), + .rx_data_10_p (rx_data_p[9]), + .rx_data_11_n (rx_data_n[6]), + .rx_data_11_p (rx_data_p[6]), + .rx_data_12_n (rx_data_n[11]), + .rx_data_12_p (rx_data_p[11]), + .rx_data_13_n (rx_data_n[12]), + .rx_data_13_p (rx_data_p[12]), + .rx_data_14_n (rx_data_n[13]), + .rx_data_14_p (rx_data_p[13]), + .rx_data_15_n (rx_data_n[14]), + .rx_data_15_p (rx_data_p[14]), + + .rx_ref_clk_0 (rx_ref_clk), + .rx_ref_clk_1 (rx_ref_clk_replica), + .glbl_clk_0 (glbl_clk_buf), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref)); + +endmodule