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cn0506_mii: Add support on zcu102

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AndreiGrozav 2019-09-24 18:44:32 +03:00 committed by AndreiGrozav
parent 3cb2392711
commit fbb3a154ff
6 changed files with 303 additions and 0 deletions
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15
projects/cn0506_mii/zcu102/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := cn0506_zcu102
M_DEPS += ../common/cn0506_bd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk

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projects/cn0506_mii/zcu102/README.rst Normal file
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- Connect to FMC1
- Voltage 1.8V
- MII mode, Connected to PS8's Ethernet 0(PHY 0) and Ethernet 1(PHY 1).

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projects/cn0506_mii/zcu102/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
# configuring one parameter at a time will end in a validation proces halt
set_property -dict [list \
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET0__GRP_MDIO__IO {EMIO} \
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET0__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET1__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET1__GRP_MDIO__IO {EMIO}] [get_bd_cells sys_ps8]
source ../common/cn0506_bd.tcl
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/GMII_ENET0]
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/MDIO_ENET0]
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/GMII_ENET1]
make_bd_intf_pins_external [get_bd_intf_pins sys_ps8/MDIO_ENET1]

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projects/cn0506_mii/zcu102/system_constr.xdc Normal file
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set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18} [get_ports mii_rx_clk_a] ; ## G06 FMC_HPC1_LA00_CC_P
set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVCMOS18} [get_ports mii_rx_er_a] ; ## D08 FMC_HPC1_LA01_CC_P
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVCMOS18} [get_ports mii_rx_dv_a] ; ## H14 FMC_HPC1_LA07_N
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_a[0]}] ; ## H07 FMC_HPC1_LA02_P
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_a[1]}] ; ## H08 FMC_HPC1_LA02_N
set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_a[2]}] ; ## G09 FMC_HPC1_LA03_P
set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_a[3]}] ; ## G10 FMC_HPC1_LA03_N
set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVCMOS18} [get_ports mii_tx_clk_a] ; ## H11 FMC_HPC1_LA04_N
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports mii_tx_en_a] ; ## H13 FMC_HPC1_LA07_P
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_a[0]}] ; ## D14 FMC_HPC1_LA09_P
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_a[1]}] ; ## D15 FMC_HPC1_LA09_N
set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_a[2]}] ; ## C10 FMC_HPC1_LA06_P
set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_a[3]}] ; ## C11 FMC_HPC1_LA06_N
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mdio_fmc_a] ; ## H16 FMC_HPC1_LA11_P
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports mdc_fmc_a] ; ## H17 FMC_HPC1_LA11_N
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports reset_a] ; ## H19 FMC_HPC1_LA15_P
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18} [get_ports link_st_a] ; ## H10 FMC_HPC1_LA04_P
set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVCMOS18} [get_ports mii_crs_a] ; ## G13 FMC_HPC1_LA08_N
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18} [get_ports led_0_a] ; ## G12 FMC_HPC1_LA08_P
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports led_ar_c_c2m] ; ## G15 FMC_HPC1_LA12_P
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports led_ar_a_c2m] ; ## G16 FMC_HPC1_LA12_N
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVCMOS18} [get_ports led_al_c_c2m] ; ## D17 FMC_HPC1_LA13_P
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVCMOS18} [get_ports led_al_a_c2m] ; ## D18 FMC_HPC1_LA13_N
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18} [get_ports mii_rx_clk_b] ; ## C22 FMC_HPC1_LA18_CC_P
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS18} [get_ports mii_rx_er_b] ; ## D20 FMC_HPC1_LA17_CC_P
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS18} [get_ports mii_rx_dv_b] ; ## H29 FMC_HPC1_LA24_N
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_b[0]}] ; ## H22 FMC_HPC1_LA19_P
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_b[1]}] ; ## H23 FMC_HPC1_LA19_N
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_b[2]}] ; ## G21 FMC_HPC1_LA20_P
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports {mii_rxd_b[3]}] ; ## G22 FMC_HPC1_LA20_N
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS18} [get_ports mii_tx_clk_b] ; ## G28 FMC_HPC1_LA25_N
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports mii_tx_en_b] ; ## H28 FMC_HPC1_LA24_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_b[0]}] ; ## H25 FMC_HPC1_LA21_P
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_b[1]}] ; ## H26 FMC_HPC1_LA21_N
set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_b[2]}] ; ## G24 FMC_HPC1_LA22_P
set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 SLEW FAST} [get_ports {mii_txd_b[3]}] ; ## G25 FMC_HPC1_LA22_N
set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports mdio_fmc_b] ; ## H31 FMC_HPC1_LA28_P
set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports mdc_fmc_b] ; ## H32 FMC_HPC1_LA28_N
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports reset_b] ; ## H20 FMC_HPC1_LA15_N
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports link_st_b] ; ## G27 FMC_HPC1_LA25_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports mii_crs_b] ; ## D24 FMC_HPC1_LA23_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports led_0_b] ; ## D23 FMC_HPC1_LA23_P
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports led_bl_c_c2m] ; ## D26 FMC_HPC1_LA26_P
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports led_bl_a_c2m] ; ## D27 FMC_HPC1_LA26_N
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports led_br_c_c2m] ; ## G18 FMC_HPC1_LA16_P
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports led_br_a_c2m] ; ## G19 FMC_HPC1_LA16_N
create_clock -name rx_clk_1 -period 40.0 [get_ports mii_rx_clk_a]
create_clock -name rx_clk_2 -period 40.0 [get_ports mii_rx_clk_b]
create_clock -name tx_clk_1 -period 40.0 [get_ports mii_tx_clk_a]
create_clock -name tx_clk_2 -period 40.0 [get_ports mii_tx_clk_b]
create_clock -name mdio_clk_a -period 400.0 [get_pins i_system_wrapper/system_i/sys_ps8/inst/emio_enet0_mdio_mdc]
create_clock -name mdio_clk_b -period 400.0 [get_pins i_system_wrapper/system_i/sys_ps8/inst/emio_enet1_mdio_mdc]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports mii_rx_clk_b]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports mii_txd_b]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports link_st_b]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mii_tx_clk_a*]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mii_tx_clk_b*]

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projects/cn0506_mii/zcu102/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project cn0506_zcu102
adi_project_files cn0506_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run cn0506_zcu102

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projects/cn0506_mii/zcu102/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
// mii interface
output reset_a,
output mdc_fmc_a,
inout mdio_fmc_a,
input [3:0] mii_rxd_a,
input mii_rx_dv_a,
input mii_rx_clk_a,
output [3:0] mii_txd_a,
input mii_rx_er_a,
output mii_tx_en_a,
input mii_tx_clk_a,
input link_st_a,
input mii_crs_a,
input led_0_a,
output reset_b,
output mdc_fmc_b,
inout mdio_fmc_b,
input [3:0] mii_rxd_b,
input mii_rx_er_b,
input mii_rx_dv_b,
input mii_rx_clk_b,
output [3:0] mii_txd_b,
output mii_tx_en_b,
input mii_tx_clk_b,
input link_st_b,
input mii_crs_b,
input led_0_b,
// LEDs
output led_ar_c_c2m,
output led_ar_a_c2m,
output led_al_c_c2m,
output led_al_a_c2m,
output led_br_c_c2m,
output led_br_a_c2m,
output led_bl_c_c2m,
output led_bl_a_c2m
);
// internal signals
wire reset;
wire [ 2:0] speed_mode_a_s;
wire [ 2:0] speed_mode_b_s;
wire [ 3:0] mii_txd_extra_a;
wire [ 3:0] mii_txd_extra_b;
wire [94:0] gpio_i;
wire [94:0] gpio_o;
assign reset_a = reset;
assign reset_b = reset;
// port a - right led (activity/status) yellow only
assign led_ar_c_c2m = led_0_a;
assign led_ar_a_c2m = 1'b0;
// port a - left led (speed mode): 10M=off, 100M=yellow
assign led_al_c_c2m = speed_mode_a_s[0];
assign led_al_a_c2m = speed_mode_a_s[1];
// port b - right led (activity/status) yellow only
assign led_br_c_c2m = led_0_b;
assign led_br_a_c2m = 1'b0;
// port a - left led (speed mode): 10M=off, 100M=yellow
assign led_bl_c_c2m = speed_mode_b_s[0];
assign led_bl_a_c2m = speed_mode_b_s[1];
assign gpio_i[94:36] = gpio_o[94:36];
assign gpio_i[35] = link_st_a;
assign gpio_i[34] = link_st_b;
assign gpio_i[33:21] = gpio_o[33:21];
assign gpio_i[ 7:0] = gpio_o[7:0];
assign gpio_bd_o = gpio_o[ 7:0];
assign gpio_i[20:8] = gpio_bd_i;
// instantiations
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (),
.spi0_csn (),
.spi0_miso (1'b0),
.spi0_mosi (),
.spi0_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.spi1_sclk (),
.reset (reset),
.GMII_ENET0_0_col(led_0_a),
.GMII_ENET0_0_crs(mii_crs_a),
.GMII_ENET0_0_rx_clk(mii_rx_clk_a),
.GMII_ENET0_0_rx_dv(mii_rx_dv_a),
.GMII_ENET0_0_rx_er(mii_rx_er_a),
.GMII_ENET0_0_rxd({4'h0,mii_rxd_a}),
.GMII_ENET0_0_tx_clk(mii_tx_clk_a),
.GMII_ENET0_0_tx_en(mii_tx_en_a),
.GMII_ENET0_0_tx_er(),
.GMII_ENET0_0_txd({mii_txd_extra_a,mii_txd_a}),
.GMII_ENET0_0_speed_mode(speed_mode_a_s),
.MDIO_ENET0_0_mdc(mdc_fmc_a),
.MDIO_ENET0_0_mdio_io(mdio_fmc_a),
.GMII_ENET1_0_col(led_0_b),
.GMII_ENET1_0_crs(mii_crs_b),
.GMII_ENET1_0_rx_clk(mii_rx_clk_b),
.GMII_ENET1_0_rx_dv(mii_rx_dv_b),
.GMII_ENET1_0_rx_er(mii_rx_er_b),
.GMII_ENET1_0_rxd({4'h0,mii_rxd_b}),
.GMII_ENET1_0_tx_clk(mii_tx_clk_b),
.GMII_ENET1_0_tx_en(mii_tx_en_b),
.GMII_ENET1_0_tx_er(),
.GMII_ENET1_0_txd({mii_txd_extra_b,mii_txd_b}),
.GMII_ENET1_0_speed_mode(speed_mode_b_s),
.MDIO_ENET1_0_mdc(mdc_fmc_b),
.MDIO_ENET1_0_mdio_io(mdio_fmc_b)
);
endmodule
// ***************************************************************************
// ***************************************************************************