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pzsdr2- update ccfmc

main
Rejeesh Kutty 2016-11-16 16:27:05 -05:00
parent 95c44b687e
commit fb5d36b250
14 changed files with 262 additions and 514 deletions
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19
projects/pzsdr2/ccbrk_cmos/system_bd.tcl
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@ -2,22 +2,5 @@
source ../common/pzsdr2_bd.tcl source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl source ../common/ccbrk_bd.tcl
## core digital interface -- cmos (1) or lvds (0) cfg_ad9361_interface CMOS
set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in
create_bd_port -dir I rx_frame_in
create_bd_port -dir I -from 11 -to 0 rx_data_in
create_bd_port -dir O tx_clk_out
create_bd_port -dir O tx_frame_out
create_bd_port -dir O -from 11 -to 0 tx_data_out
ad_connect rx_clk_in axi_ad9361/rx_clk_in
ad_connect rx_frame_in axi_ad9361/rx_frame_in
ad_connect rx_data_in axi_ad9361/rx_data_in
ad_connect tx_clk_out axi_ad9361/tx_clk_out
ad_connect tx_frame_out axi_ad9361/tx_frame_out
ad_connect tx_data_out axi_ad9361/tx_data_out

31
projects/pzsdr2/ccbrk_lvds/system_bd.tcl
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@ -2,34 +2,5 @@
source ../common/pzsdr2_bd.tcl source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl source ../common/ccbrk_bd.tcl
## core digital interface -- cmos (1) or lvds (0) cfg_ad9361_interface LVDS
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in_p
create_bd_port -dir I rx_clk_in_n
create_bd_port -dir I rx_frame_in_p
create_bd_port -dir I rx_frame_in_n
create_bd_port -dir I -from 5 -to 0 rx_data_in_p
create_bd_port -dir I -from 5 -to 0 rx_data_in_n
create_bd_port -dir O tx_clk_out_p
create_bd_port -dir O tx_clk_out_n
create_bd_port -dir O tx_frame_out_p
create_bd_port -dir O tx_frame_out_n
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n

18
projects/pzsdr2/ccfmc_lvds/Makefile
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@ -7,19 +7,15 @@
M_DEPS += system_top.v M_DEPS += system_top.v
M_DEPS += system_project.tcl M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl M_DEPS += system_bd.tcl
M_DEPS += ../common/pzsdr2_constr_lvds.xdc
M_DEPS += ../common/pzsdr2_constr.xdc
M_DEPS += ../common/pzsdr2_bd.tcl
M_DEPS += ../common/ccfmc_constr.xdc
M_DEPS += ../common/ccfmc_bd.tcl M_DEPS += ../common/ccfmc_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
M_DEPS += ../../common/xilinx/sys_wfifo.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
M_DEPS += ../../common/pzsdr/pzsdr_bd_system_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
@ -53,7 +49,7 @@ M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all .PHONY: all lib clean clean-all
all: lib ccfmc_lvds_pzsdr.sdk/system_top.hdf all: lib pzsdr2_ccfmc_lvds.sdk/system_top.hdf
clean: clean:
@ -75,9 +71,9 @@ clean-all:clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
ccfmc_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS) pzsdr2_ccfmc_lvds.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST) -rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ccfmc_lvds_pzsdr_vivado.log 2>&1 $(M_VIVADO) system_project.tcl >> pzsdr2_ccfmc_lvds_vivado.log 2>&1
lib: lib:

4
projects/pzsdr2/ccfmc_lvds/system_bd.tcl
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@ -1,4 +1,6 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl source ../common/pzsdr2_bd.tcl
source ../common/ccfmc_bd.tcl source ../common/ccfmc_bd.tcl
cfg_ad9361_interface LVDS

247
projects/pzsdr2/ccfmc_lvds/system_constr.xdc
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@ -1,247 +0,0 @@
# rf-board
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## IO_25_VRP_34
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0] ; ## IO_L20_13_JX2_P
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1] ; ## IO_L20_13_JX2_N
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2] ; ## IO_L22_12_JX2_N
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gpio_rf3] ; ## IO_L05_34_JX4_N
# ethernet-1
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## IO_L16P_T2_34
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## IO_L16N_T2_34
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## IO_L12N_T1_MRCC_34
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## IO_L10P_T1_34
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## IO_L10N_T1_34
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## IO_L11P_T1_SRCC_34
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## IO_L11N_T1_SRCC_34
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## IO_L14N_T2_SRCC_34
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## IO_L15N_T2_DQS_34
# hdmi
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] ; ## IO_L11P_T1_SRCC_33
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] ; ## IO_L2P_T0_33
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] ; ## IO_L2N_T0_33
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] ; ## IO_L11N_T1_SRCC_33
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] ; ## IO_L3P_T0_DQS_33
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] ; ## IO_L3N_T0_DQS_33
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] ; ## IO_L4P_T0_33
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] ; ## IO_L4N_T0_33
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] ; ## IO_L5P_T0_33
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] ; ## IO_L5N_T0_33
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] ; ## IO_L6P_T0_33
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] ; ## IO_L6N_T0_VREF_33
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] ; ## IO_L7P_T1_33
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] ; ## IO_L7N_T1_33
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] ; ## IO_L8P_T1_33
set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] ; ## IO_L8N_T1_33
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] ; ## IO_L9P_T1_DQS_33
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] ; ## IO_L9N_T1_DQS_33
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] ; ## IO_L10P_T1_33
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] ; ## IO_L10N_T1_33
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports hdmi_pd] ; ## IO_0_VRN_33
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports hdmi_intn] ; ## IO_25_VRP_33
# hdmi-spdif
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports spdif] ; ## IO_L1P_T0_33
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports spdif_in] ; ## IO_L1N_T0_33
# audio
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] ; ## IO_L6P_T0_34
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] ; ## IO_L6N_T0_VREF_34
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] ; ## IO_L7P_T1_34
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] ; ## IO_L7N_T1_34
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] ; ## IO_L8P_T1_34
# ad9517
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9517_csn] ; ## IO_L20N_T3_34
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9517_clk] ; ## IO_L19P_T3_34
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9517_mosi] ; ## IO_L19N_T3_VREF_34
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9517_miso] ; ## IO_L20P_T3_34
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9517_pdn] ; ## IO_L21P_T3_DQS_34
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel] ; ## IO_L21N_T3_DQS_34
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9517_ld] ; ## IO_L22P_T3_34
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9517_status] ; ## IO_L22N_T3_34
# clocks
create_clock -period 8.000 -name eth1_rgmii_rxclk [get_ports eth1_rgmii_rxclk]
# bad ip- we have to do this
set_property IDELAY_VALUE 16 \
[get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
[get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
[get_cells -hier -filter {name =~ *idelayctrl}] \
[get_cells -hier -filter {name =~ *delay_rgmii_rxd*}] \
[get_cells -hier -filter {name =~ *delay_rgmii_rx_ctl}]
# fan control/sense
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports fan_pwm] ; ## IO_L18P_T2_34
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports fan_tach] ; ## IO_L18N_T2_34
# unused io (gpio/gt)
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p] ; ## IO_L13P_T2_MRCC_12 (fmc_clk0_p)
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n] ; ## IO_L13N_T2_MRCC_12 (fmc_clk0_n)
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p)
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n)
set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p)
set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n)
set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111 (fmc_gt_tx_p)
set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111 (fmc_gt_tx_n)
set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111 (fmc_gt_rx_p)
set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111 (fmc_gt_rx_n)
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in_0] ; ## IO_25_13 (fmc_prstn)
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## IO_L12P_T1_MRCC_12 (fmc_la_p[ 0])
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## IO_L12N_T1_MRCC_12 (fmc_la_n[ 0])
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## IO_L11P_T1_SRCC_12 (fmc_la_p[ 1])
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## IO_L11N_T1_SRCC_12 (fmc_la_n[ 1])
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## IO_L1P_T0_12 (fmc_la_p[ 2])
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## IO_L1N_T0_12 (fmc_la_n[ 2])
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## IO_L2P_T0_12 (fmc_la_p[ 3])
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## IO_L2N_T0_12 (fmc_la_n[ 3])
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## IO_L3P_T0_DQS_12 (fmc_la_p[ 4])
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## IO_L3N_T0_DQS_12 (fmc_la_n[ 4])
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## IO_L4P_T0_12 (fmc_la_p[ 5])
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## IO_L4N_T0_12 (fmc_la_n[ 5])
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## IO_L5P_T0_12 (fmc_la_p[ 6])
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## IO_L5N_T0_12 (fmc_la_n[ 6])
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## IO_L6P_T0_12 (fmc_la_p[ 7])
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## IO_L6N_T0_VREF_12 (fmc_la_n[ 7])
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## IO_L7P_T1_12 (fmc_la_p[ 8])
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## IO_L7N_T1_12 (fmc_la_n[ 8])
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## IO_L8P_T1_12 (fmc_la_p[ 9])
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## IO_L8N_T1_12 (fmc_la_n[ 9])
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## IO_L9P_T1_DQS_12 (fmc_la_p[10])
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## IO_L9N_T1_DQS_12 (fmc_la_n[10])
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## IO_L10P_T1_12 (fmc_la_p[11])
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## IO_L10N_T1_12 (fmc_la_n[11])
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## IO_L14P_T2_SRCC_12 (fmc_la_p[12])
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## IO_L14N_T2_SRCC_12 (fmc_la_n[12])
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## IO_L15P_T2_DQS_12 (fmc_la_p[13])
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_out[27]] ; ## IO_L15N_T2_DQS_12 (fmc_la_n[13])
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_out[28]] ; ## IO_L16P_T2_12 (fmc_la_p[14])
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_out[29]] ; ## IO_L16N_T2_12 (fmc_la_n[14])
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_out[30]] ; ## IO_L17P_T2_12 (fmc_la_p[15])
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_out[31]] ; ## IO_L17N_T2_12 (fmc_la_n[15])
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_out[32]] ; ## IO_L18P_T2_12 (fmc_la_p[16])
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_out[33]] ; ## IO_L18N_T2_12 (fmc_la_n[16])
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## IO_L12P_T1_MRCC_13 (fmc_la_p[17])
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## IO_L12N_T1_MRCC_13 (fmc_la_n[17])
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## IO_L11P_T1_SRCC_13 (fmc_la_p[18])
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## IO_L11N_T1_SRCC_13 (fmc_la_n[18])
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## IO_L1P_T0_13 (fmc_la_p[19])
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## IO_L1N_T0_13 (fmc_la_n[19])
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## IO_L2P_T0_13 (fmc_la_p[20])
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## IO_L2N_T0_13 (fmc_la_n[20])
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## IO_L3P_T0_DQS_13 (fmc_la_p[21])
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## IO_L3N_T0_DQS_13 (fmc_la_n[21])
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## IO_L4P_T0_13 (fmc_la_p[22])
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## IO_L4N_T0_13 (fmc_la_n[22])
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## IO_L6P_T0_13 (fmc_la_p[23])
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## IO_L6N_T0_VREF_13 (fmc_la_n[23])
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## IO_L7P_T1_13 (fmc_la_p[24])
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## IO_L7N_T1_13 (fmc_la_n[24])
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## IO_L8P_T1_13 (fmc_la_p[25])
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## IO_L8N_T1_13 (fmc_la_n[25])
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## IO_L9P_T1_DQS_13 (fmc_la_p[26])
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## IO_L9N_T1_DQS_13 (fmc_la_n[26])
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## IO_L10P_T1_13 (fmc_la_p[27])
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## IO_L10N_T1_13 (fmc_la_n[27])
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## IO_L14P_T2_SRCC_13 (fmc_la_p[28])
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## IO_L14N_T2_SRCC_13 (fmc_la_n[28])
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## IO_L15P_T2_DQS_13 (fmc_la_p[29])
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## IO_L15N_T2_DQS_13 (fmc_la_n[29])
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## IO_L16P_T2_13 (fmc_la_p[30])
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_in[27]] ; ## IO_L16N_T2_13 (fmc_la_n[30])
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_in[28]] ; ## IO_L17P_T2_13 (fmc_la_p[31])
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_in[29]] ; ## IO_L17N_T2_13 (fmc_la_n[31])
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_in[30]] ; ## IO_L18P_T2_13 (fmc_la_p[32])
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_in[31]] ; ## IO_L18N_T2_13 (fmc_la_n[32])
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32]] ; ## IO_L19P_T3_13 (fmc_la_p[33])
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## IO_L19N_T3_VREF_13 (fmc_la_n[33])
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## IO_L21P_T3_DQS_13 (pmod0[0])
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L21N_T3_DQS_13 (pmod0[1])
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## IO_L22P_T3_13 (pmod0[2])
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## IO_L22N_T3_13 (pmod0[3])
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## IO_L23P_T3_13 (pmod0[4])
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC)
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## IO_L24P_T3_13 (pmod0[6])
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## IO_L24N_T3_13 (pmod0[7])
set_property -dict {PACKAGE_PIN AA6} [get_ports clk_2_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p)
set_property -dict {PACKAGE_PIN AA5} [get_ports clk_2_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n)
set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111 (sfp_gt_tx_p)
set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111 (sfp_gt_tx_n)
set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111 (sfp_gt_rx_p)
set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111 (sfp_gt_rx_n)
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L1P_T0_34 (CAM_GPIO_0 )
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L1N_T0_34 (CAM_GPIO_1 )
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports gp_in[39]] ; ## IO_L3P_T0_DQS_PUDC_B_34 (CAM_GPIO_4 )
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports gp_in[40]] ; ## IO_L3N_T0_DQS_34 (CAM_GPIO_5 )
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS18} [get_ports gp_in[41]] ; ## IO_L13P_T2_MRCC_33 (CAM_CLK_P )
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS18} [get_ports gp_in[42]] ; ## IO_L13N_T2_MRCC_33 (CAM_CLK_N )
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS18} [get_ports gp_in[43]] ; ## IO_L16P_T2_33 (CAM_DATA1_P )
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports gp_in[44]] ; ## IO_L16N_T2_33 (CAM_DATA1_N )
set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS18} [get_ports gp_in[45]] ; ## IO_L18P_T2_33 (CAM_DATA3_P )
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS18} [get_ports gp_in[46]] ; ## IO_L18N_T2_33 (CAM_DATA3_N )
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports gp_in[47]] ; ## IO_L20P_T3_33 (CAM_DATA5_P )
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports gp_in[48]] ; ## IO_L20N_T3_33 (CAM_DATA5_N )
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports gp_in[49]] ; ## IO_L22P_T3_33 (CAM_DATA7_P )
set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[50]] ; ## IO_L22N_T3_33 (CAM_DATA7_N )
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## IO_L23P_T3_33 (CAM_SPI_CSN )
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## IO_L23N_T3_33 (CAM_SPI_CLK )
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## IO_L12P_T1_MRCC_33 (CAM_REFCLK )
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports gp_out[37]] ; ## IO_L2P_T0_34 (CAM_GPIO_2 )
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports gp_out[38]] ; ## IO_L2N_T0_34 (CAM_GPIO_3 )
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports gp_out[39]] ; ## IO_L4P_T0_34 (CAM_GPIO_6 )
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports gp_out[40]] ; ## IO_L4N_T0_34 (CAM_GPIO_7 )
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS18} [get_ports gp_out[41]] ; ## IO_L15P_T2_DQS_33 (CAM_DATA0_P )
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS18} [get_ports gp_out[42]] ; ## IO_L15N_T2_DQS_33 (CAM_DATA0_N )
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS18} [get_ports gp_out[43]] ; ## IO_L17P_T2_33 (CAM_DATA2_P )
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS18} [get_ports gp_out[44]] ; ## IO_L17N_T2_33 (CAM_DATA2_N )
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports gp_out[45]] ; ## IO_L19P_T3_33 (CAM_DATA4_P )
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports gp_out[46]] ; ## IO_L19N_T3_VREF_33 (CAM_DATA4_N )
set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS18} [get_ports gp_out[47]] ; ## IO_L21P_T3_DQS_33 (CAM_DATA6_P )
set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports gp_out[48]] ; ## IO_L21N_T3_DQS_33 (CAM_DATA6_N )
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS18} [get_ports gp_out[49]] ; ## IO_L14P_T2_SRCC_33 (CAM_SYNC_P )
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports gp_out[50]] ; ## IO_L14N_T2_SRCC_33 (CAM_SYNC_N )
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports gp_out[51]] ; ## IO_L24P_T3_33 (CAM_SPI_MISO)
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports gp_out[52]] ; ## IO_L24N_T3_33 (CAM_SPI_MOSI)
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports gp_out[53]] ; ## IO_L5P_T0_34 (CAM_GPIO_8 )
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_inout[0]] ; ## IO_L19P_T3_12 (sfp_gpio[0])
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_inout[1]] ; ## IO_L19N_T3_VREF_12 (sfp_gpio[1])
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_inout[2]] ; ## IO_L20P_T3_12 (sfp_gpio[2])
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_inout[3]] ; ## IO_L20N_T3_12 (sfp_gpio[3])
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_inout[4]] ; ## IO_L21P_T3_DQS_12 (sfp_gpio[4])
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_inout[5]] ; ## IO_L21N_T3_DQS_12 (sfp_gpio[5])
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_inout[6]] ; ## IO_L22P_T3_12 (sfp_gpio[6])
# clocks
create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]

16
projects/pzsdr2/ccfmc_lvds/system_project.tcl
View File

@ -3,15 +3,15 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccfmc_lvds_pzsdr set p_device "xc7z035ifbg676-2L"
adi_project_files ccfmc_lvds_pzsdr [list \ adi_project_create pzsdr2_ccfmc_lvds
"system_top.v" \ adi_project_files pzsdr2_ccfmc_lvds [list \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \ "../common/pzsdr2_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \ "../common/pzsdr2_constr_lvds.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ] "../common/ccfmc_constr.xdc" \
"system_top.v" ]
adi_project_run ccfmc_lvds_pzsdr adi_project_run pzsdr2_ccfmc_lvds

80
projects/pzsdr2/ccfmc_lvds/system_top.v
View File

@ -91,7 +91,7 @@ module system_top (
inout iic_scl, inout iic_scl,
inout iic_sda, inout iic_sda,
inout [11:0] gpio_bd, inout [20:0] gpio_bd,
output fan_pwm, output fan_pwm,
input fan_tach, input fan_tach,
@ -100,16 +100,13 @@ module system_top (
input clk_0_n, input clk_0_n,
input clk_1_p, input clk_1_p,
input clk_1_n, input clk_1_n,
input clk_2_p,
input clk_2_n,
input gp_in_0,
input gp_in_1,
inout [ 6:0] gp_inout,
output [53:0] gp_out, output [53:0] gp_out,
input [53:0] gp_in, input [53:0] gp_in,
input gt_ref_clk_p, input gt_ref_clk_0_p,
input gt_ref_clk_n, input gt_ref_clk_0_n,
input gt_ref_clk_1_p,
input gt_ref_clk_1_n,
output [ 1:0] gt_tx_p, output [ 1:0] gt_tx_p,
output [ 1:0] gt_tx_n, output [ 1:0] gt_tx_n,
input [ 1:0] gt_rx_p, input [ 1:0] gt_rx_p,
@ -139,13 +136,14 @@ module system_top (
output enable, output enable,
output txnrx, output txnrx,
input clk_out, input clkout_in,
inout tdd_sync, inout tdd_sync,
inout gpio_rf0, inout gpio_rf0,
inout gpio_rf1, inout gpio_rf1,
inout gpio_rf2, inout gpio_rf2,
inout gpio_rf3, inout gpio_rf3,
inout gpio_rf4,
inout gpio_rfpwr_enable, inout gpio_rfpwr_enable,
inout gpio_clksel, inout gpio_clksel,
inout gpio_resetb, inout gpio_resetb,
@ -167,13 +165,10 @@ module system_top (
wire spi_miso_s; wire spi_miso_s;
wire clk_0; wire clk_0;
wire clk_1; wire clk_1;
wire clk_2; wire gt_ref_clk_1;
wire gt_ref_clk; wire gt_ref_clk_0;
wire [63:0] gp_out_s; wire [63:0] gp_out_s;
wire [63:0] gp_in_s; wire [63:0] gp_in_s;
wire [63:0] gp_misc_out_s;
wire [63:0] gp_misc_in_s;
wire [63:0] gp_misc_ioenb_s;
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
@ -193,10 +188,6 @@ module system_top (
assign ad9517_mosi = spi_mosi_s; assign ad9517_mosi = spi_mosi_s;
assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso);
assign gp_misc_in_s[63:10] = gp_misc_out_s[63:18];
assign gp_misc_in_s[9] = gp_in_1;
assign gp_misc_in_s[8] = gp_in_0;
assign gp_misc_in_s[7] = gp_misc_out_s[7];
assign gp_out[53:0] = gp_out_s[53:0]; assign gp_out[53:0] = gp_out_s[53:0];
assign gp_in_s[63:54] = gp_out_s[63:54]; assign gp_in_s[63:54] = gp_out_s[63:54];
@ -214,37 +205,32 @@ module system_top (
.IB (clk_1_n), .IB (clk_1_n),
.O (clk_1)); .O (clk_1));
IBUFDS_GTE2 i_ibufds_clk_2 ( IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 (
.CEB (1'd0), .CEB (1'd0),
.I (clk_2_p), .I (gt_ref_clk_0_p),
.IB (clk_2_n), .IB (gt_ref_clk_0_n),
.O (clk_2), .O (gt_ref_clk_0),
.ODIV2 ()); .ODIV2 ());
IBUFDS_GTE2 i_ibufds_gt_ref_clk ( IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 (
.CEB (1'd0), .CEB (1'd0),
.I (gt_ref_clk_p), .I (gt_ref_clk_1_p),
.IB (gt_ref_clk_n), .IB (gt_ref_clk_1_n),
.O (gt_ref_clk), .O (gt_ref_clk_1),
.ODIV2 ()); .ODIV2 ());
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_sfp (
.dio_t (gp_misc_ioenb_s[6:0]),
.dio_i (gp_misc_out_s[6:0]),
.dio_o (gp_misc_in_s[6:0]),
.dio_p (gp_inout));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
.dio_t (tdd_sync_t), .dio_t (tdd_sync_t),
.dio_i (tdd_sync_o), .dio_i (tdd_sync_o),
.dio_o (tdd_sync_i), .dio_o (tdd_sync_i),
.dio_p (tdd_sync)); .dio_p (tdd_sync));
ad_iobuf #(.DATA_WIDTH(25)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(26)) i_iobuf (
.dio_t ({gpio_t[60:51], gpio_t[46:32]}), .dio_t ({gpio_t[61:51], gpio_t[46:32]}),
.dio_i ({gpio_o[60:51], gpio_o[46:32]}), .dio_i ({gpio_o[61:51], gpio_o[46:32]}),
.dio_o ({gpio_i[60:51], gpio_i[46:32]}), .dio_o ({gpio_i[61:51], gpio_i[46:32]}),
.dio_p ({ ad9517_pdn, // 60:60 .dio_p ({ gpio_rf4, // 61:61
ad9517_pdn, // 60:60
ad9517_ref_sel, // 59:59 ad9517_ref_sel, // 59:59
ad9517_ld, // 58:58 ad9517_ld, // 58:58
ad9517_status, // 57:57 ad9517_status, // 57:57
@ -260,16 +246,15 @@ module system_top (
gpio_ctl, // 43:40 gpio_ctl, // 43:40
gpio_status})); // 39:32 gpio_status})); // 39:32
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
.dio_t (gpio_t[11:0]), .dio_t (gpio_t[20:0]),
.dio_i (gpio_o[11:0]), .dio_i (gpio_o[20:0]),
.dio_o (gpio_i[11:0]), .dio_o (gpio_i[20:0]),
.dio_p (gpio_bd)); .dio_p (gpio_bd));
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.clk_0 (clk_0), .clk_0 (clk_0),
.clk_1 (clk_1), .clk_1 (clk_1),
.clk_2 (clk_2),
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
.ddr_ba (ddr_ba), .ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n), .ddr_cas_n (ddr_cas_n),
@ -303,20 +288,13 @@ module system_top (
.fixed_io_ps_srstb (fixed_io_ps_srstb), .fixed_io_ps_srstb (fixed_io_ps_srstb),
.gp_in_0 (gp_in_s[31:0]), .gp_in_0 (gp_in_s[31:0]),
.gp_in_1 (gp_in_s[63:32]), .gp_in_1 (gp_in_s[63:32]),
.gp_in_2 (gp_misc_in_s[31:0]),
.gp_in_3 (gp_misc_in_s[63:32]),
.gp_ioenb_0 (),
.gp_ioenb_1 (),
.gp_ioenb_2 (gp_misc_ioenb_s[31:0]),
.gp_ioenb_3 (gp_misc_ioenb_s[63:32]),
.gp_out_0 (gp_out_s[31:0]), .gp_out_0 (gp_out_s[31:0]),
.gp_out_1 (gp_out_s[63:32]), .gp_out_1 (gp_out_s[63:32]),
.gp_out_2 (gp_misc_out_s[31:0]),
.gp_out_3 (gp_misc_out_s[63:32]),
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
.gt_ref_clk (gt_ref_clk), .gt_ref_clk_0 (gt_ref_clk_0),
.gt_ref_clk_1 (gt_ref_clk_1),
.gt_rx_n (gt_rx_n), .gt_rx_n (gt_rx_n),
.gt_rx_p (gt_rx_p), .gt_rx_p (gt_rx_p),
.gt_tx_n (gt_tx_n), .gt_tx_n (gt_tx_n),

17
projects/pzsdr2/ccpci_lvds/Makefile
View File

@ -7,18 +7,15 @@
M_DEPS += system_top.v M_DEPS += system_top.v
M_DEPS += system_project.tcl M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl M_DEPS += system_bd.tcl
M_DEPS += ../common/pzsdr2_constr_lvds.xdc
M_DEPS += ../common/pzsdr2_constr.xdc
M_DEPS += ../common/pzsdr2_bd.tcl
M_DEPS += ../common/ccpci_constr.xdc
M_DEPS += ../common/ccpci_bd.tcl M_DEPS += ../common/ccpci_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
M_DEPS += ../../common/xilinx/sys_wfifo.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@ -46,7 +43,7 @@ M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all .PHONY: all lib clean clean-all
all: lib ccpci_lvds_pzsdr.sdk/system_top.hdf all: lib pzsdr2_ccpci_lvds.sdk/system_top.hdf
clean: clean:
@ -62,9 +59,9 @@ clean-all:clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
ccpci_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS) pzsdr2_ccpci_lvds.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST) -rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ccpci_lvds_pzsdr_vivado.log 2>&1 $(M_VIVADO) system_project.tcl >> pzsdr2_ccpci_lvds_vivado.log 2>&1
lib: lib:

36
projects/pzsdr2/ccpci_lvds/system_bd.tcl
View File

@ -1,10 +1,36 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl source ../common/pzsdr2_bd.tcl
source ../common/ccpci_bd.tcl source ../common/ccpci_bd.tcl
## temporary ## core digital interface -- cmos (1) or lvds (0)
## ila
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in_p
create_bd_port -dir I rx_clk_in_n
create_bd_port -dir I rx_frame_in_p
create_bd_port -dir I rx_frame_in_n
create_bd_port -dir I -from 5 -to 0 rx_data_in_p
create_bd_port -dir I -from 5 -to 0 rx_data_in_n
create_bd_port -dir O tx_clk_out_p
create_bd_port -dir O tx_clk_out_n
create_bd_port -dir O tx_frame_out_p
create_bd_port -dir O tx_frame_out_n
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
delete_bd_objs [get_bd_cells ila_adc]
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]

20
projects/pzsdr2/ccpci_lvds/system_project.tcl
View File

@ -1,21 +1,17 @@
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccpci_lvds_pzsdr set p_device "xc7z035ifbg676-2L"
adi_project_files ccpci_lvds_pzsdr [list \ adi_project_create pzsdr2_ccpci_lvds
"system_top.v" \ adi_project_files pzsdr2_ccpci_lvds [list \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \ "../common/pzsdr2_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ] "../common/pzsdr2_constr_lvds.xdc" \
"../common/ccpci_constr.xdc" \
"system_top.v" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] adi_project_run pzsdr2_ccpci_lvds
set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
adi_project_run ccpci_lvds_pzsdr

196
projects/pzsdr2/common/ccbrk_constr.xdc
View File

@ -11,19 +11,19 @@ set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (lb: gpio_bd[6]) U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26 set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (lb: gpio_bd[6]) U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (lb: gpio_bd[12]) U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28 set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (lb: gpio_bd[12]) U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (lb: gpio_bd[0]) U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16 set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (lb: gpio_bd[0]) U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## (lb: gpio_bd[1]) U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3 set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (lb: gpio_bd[1]) U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2,P13,3
set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## (lb: gpio_bd[2]) U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4 set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (lb: gpio_bd[2]) U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1,P13,4
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## (lb: i2c_scl) U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14) set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (lb: i2c_scl) U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 (U1,AF24,SCL,JX2,17,I2C_SCL,P2,14)
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## (lb: none) U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0 set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## (lb: none) U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## (lb: none) U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1 set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## (lb: none) U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## (lb: none) U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2 set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## (lb: none) U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## (lb: none) U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3 set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## (lb: none) U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
## orphans- io- (ps7 gpio) ## orphans- io- (ps7 gpio)
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## (lb: gpio_bd[3]) U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3 set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## (lb: gpio_bd[3]) U1,V18,IO_25_13_JX2,JX2,14,IO_25_13_JX2,P2,3
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## (lb: i2c_sda) U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16) set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## (lb: i2c_sda) U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 (U1,AF25,SDA,JX2,19,I2C_SDA,P2,16)
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## (lb: none) U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## (lb: none) U1,AA24,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## (lb: clkout_out) U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31 set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## (lb: clkout_out) U1,N8,IO_25_33_JX1,JX1,10,IO_25_33_JX1,P7,31
## ps7- fixed io- to- fpga regular io (ps7 gpio) ## ps7- fixed io- to- fpga regular io (ps7 gpio)
@ -43,50 +43,50 @@ set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gpio
## fpga- regular io ## fpga- regular io
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6 set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports gp_out[0]] ; ## U1,AA25,IO_L01_13_JX2_P,JX2,1,IO_L01_13_JX2_P,P2,6
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports gp_in[0]] ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5 set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports gp_in[0]] ; ## U1,AB26,IO_L02_13_JX2_P,JX2,2,IO_L02_13_JX2_P,P2,5
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports gp_out[1]] ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8 set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports gp_out[1]] ; ## U1,AB25,IO_L01_13_JX2_N,JX2,3,IO_L01_13_JX2_N,P2,8
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports gp_in[1]] ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7 set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports gp_in[1]] ; ## U1,AC26,IO_L02_13_JX2_N,JX2,4,IO_L02_13_JX2_N,P2,7
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS18} [get_ports gp_out[2]] ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10 set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gp_out[2]] ; ## U1,AE25,IO_L03_13_JX2_P,JX2,5,IO_L03_13_JX2_P,P2,10
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS18} [get_ports gp_in[2]] ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9 set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gp_in[2]] ; ## U1,AD25,IO_L04_13_JX2_P,JX2,6,IO_L04_13_JX2_P,P2,9
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS18} [get_ports gp_out[3]] ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12 set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports gp_out[3]] ; ## U1,AE26,IO_L03_13_JX2_N,JX2,7,IO_L03_13_JX2_N,P2,12
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS18} [get_ports gp_in[3]] ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11 set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gp_in[3]] ; ## U1,AD26,IO_L04_13_JX2_N,JX2,8,IO_L04_13_JX2_N,P2,11
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS18} [get_ports gp_out[4]] ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20 set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports gp_out[4]] ; ## U1,AE22,IO_L07_13_JX2_P,JX2,23,IO_L07_13_JX2_P,P2,20
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS18} [get_ports gp_in[4]] ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19 set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports gp_in[4]] ; ## U1,AE23,IO_L08_13_JX2_P,JX2,24,IO_L08_13_JX2_P,P2,19
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS18} [get_ports gp_out[5]] ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22 set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports gp_out[5]] ; ## U1,AF22,IO_L07_13_JX2_N,JX2,25,IO_L07_13_JX2_N,P2,22
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS18} [get_ports gp_in[5]] ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21 set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports gp_in[5]] ; ## U1,AF23,IO_L08_13_JX2_N,JX2,26,IO_L08_13_JX2_N,P2,21
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports gp_out[6]] ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24 set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports gp_out[6]] ; ## U1,AB21,IO_L09_13_JX2_P,JX2,29,IO_L09_13_JX2_P,P2,24
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports gp_in[6]] ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23 set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports gp_in[6]] ; ## U1,AA22,IO_L10_13_JX2_P,JX2,30,IO_L10_13_JX2_P,P2,23
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS18} [get_ports gp_out[7]] ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26 set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports gp_out[7]] ; ## U1,AB22,IO_L09_13_JX2_N,JX2,31,IO_L09_13_JX2_N,P2,26
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports gp_in[7]] ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25 set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports gp_in[7]] ; ## U1,AA23,IO_L10_13_JX2_N,JX2,32,IO_L10_13_JX2_N,P2,25
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports gp_out[8]] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28 set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports gp_out[8]] ; ## U1,AD23,IO_L11_SRCC_13_JX2_P,JX2,35,IO_L11_SRCC_13_JX2_P,P2,28
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports gp_in[8]] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27 set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports gp_in[8]] ; ## U1,AC23,IO_L12_MRCC_13_JX2_P,JX2,36,IO_L12_MRCC_13_JX2_P,P2,27
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports gp_out[9]] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30 set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports gp_out[9]] ; ## U1,AD24,IO_L11_SRCC_13_JX2_N,JX2,37,IO_L11_SRCC_13_JX2_N,P2,30
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports gp_in[9]] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29 set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports gp_in[9]] ; ## U1,AC24,IO_L12_MRCC_13_JX2_N,JX2,38,IO_L12_MRCC_13_JX2_N,P2,29
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports gp_out[10]] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32 set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS25} [get_ports gp_out[10]] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,IO_L13_MRCC_13_JX2_P,P2,32
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports gp_in[10]] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31 set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports gp_in[10]] ; ## U1,AC21,IO_L14_SRCC_13_JX2_P,JX2,42,IO_L14_SRCC_13_JX2_P,P2,31
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports gp_out[11]] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34 set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports gp_out[11]] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,IO_L13_MRCC_13_JX2_N,P2,34
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports gp_in[11]] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33 set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gp_in[11]] ; ## U1,AC22,IO_L14_SRCC_13_JX2_N,JX2,44,IO_L14_SRCC_13_JX2_N,P2,33
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports gp_out[12]] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38 set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports gp_out[12]] ; ## U1,AF19,IO_L15_13_JX2_P,JX2,47,IO_L15_13_JX2_P,P2,38
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports gp_in[12]] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37 set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports gp_in[12]] ; ## U1,AE20,IO_L16_13_JX2_P,JX2,48,IO_L16_13_JX2_P,P2,37
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports gp_out[13]] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40 set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports gp_out[13]] ; ## U1,AF20,IO_L15_13_JX2_N,JX2,49,IO_L15_13_JX2_N,P2,40
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS18} [get_ports gp_in[13]] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39 set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports gp_in[13]] ; ## U1,AE21,IO_L16_13_JX2_N,JX2,50,IO_L16_13_JX2_N,P2,39
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports gp_out[14]] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42 set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports gp_out[14]] ; ## U1,AD18,IO_L17_13_JX2_P,JX2,53,IO_L17_13_JX2_P,P2,42
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS18} [get_ports gp_in[14]] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41 set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gp_in[14]] ; ## U1,AE18,IO_L18_13_JX2_P,JX2,54,IO_L18_13_JX2_P,P2,41
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports gp_out[15]] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44 set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports gp_out[15]] ; ## U1,AD19,IO_L17_13_JX2_N,JX2,55,IO_L17_13_JX2_N,P2,44
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS18} [get_ports gp_in[15]] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43 set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports gp_in[15]] ; ## U1,AF18,IO_L18_13_JX2_N,JX2,56,IO_L18_13_JX2_N,P2,43
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports gp_out[16]] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46 set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_out[16]] ; ## U1,W20,IO_L19_13_JX2_P,JX2,61,IO_L19_13_JX2_P,P2,46
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS18} [get_ports gp_in[16]] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45 set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gp_in[16]] ; ## U1,AA20,IO_L20_13_JX2_P,JX2,62,IO_L20_13_JX2_P,P2,45
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports gp_out[17]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48 set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_out[17]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,IO_L19_13_JX2_N,P2,48
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports gp_in[17]] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47 set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gp_in[17]] ; ## U1,AB20,IO_L20_13_JX2_N,JX2,64,IO_L20_13_JX2_N,P2,47
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS18} [get_ports gp_out[18]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52 set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[18]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS18} [get_ports gp_in[18]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51 set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_in[18]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,IO_L22_13_JX2_P,P2,51
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS18} [get_ports gp_out[19]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54 set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_out[19]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS18} [get_ports gp_in[19]] ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53 set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_in[19]] ; ## U1,AB19,IO_L22_13_JX2_N,JX2,70,IO_L22_13_JX2_N,P2,53
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports gp_out[20]] ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56 set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_out[20]] ; ## U1,W18,IO_L23_13_JX2_P,JX2,73,IO_L23_13_JX2_P,P2,56
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports gp_in[20]] ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55 set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,Y18,IO_L24_13_JX2_P,JX2,74,IO_L24_13_JX2_P,P2,55
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports gp_out[21]] ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58 set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,W19,IO_L23_13_JX2_N,JX2,75,IO_L23_13_JX2_N,P2,58
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS18} [get_ports gp_in[21]] ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57 set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,AA18,IO_L24_13_JX2_N,JX2,76,IO_L24_13_JX2_N,P2,57
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2 set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,IO_L01_33_JX1_P,P4,2
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1 set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,IO_L02_33_JX1_P,P4,1
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4 set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,IO_L01_33_JX1_N,P4,4
@ -171,50 +171,50 @@ set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports gp_o
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_in[62]] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27 set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports gp_in[62]] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_out[63]] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30 set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports gp_out[63]] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_in[63]] ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29 set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports gp_in[63]] ; ## U1,L9,IO_00_33_JX1,JX1,9,IO_00_33_JX1,P7,29
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS18} [get_ports gp_out[64]] ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6 set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports gp_out[64]] ; ## U1,AD15,IO_L15_12_JX3_N,JX3,99,IO_L15_12_JX3_N,P13,6
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS18} [get_ports gp_in[64]] ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5 set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports gp_in[64]] ; ## U1,AF14,IO_L16_12_JX3_N,JX3,100,IO_L16_12_JX3_N,P13,5
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS18} [get_ports gp_out[65]] ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8 set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports gp_out[65]] ; ## U1,AD16,IO_L15_12_JX3_P,JX3,97,IO_L15_12_JX3_P,P13,8
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS18} [get_ports gp_in[65]] ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7 set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gp_in[65]] ; ## U1,AF15,IO_L16_12_JX3_P,JX3,98,IO_L16_12_JX3_P,P13,7
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS18} [get_ports gp_out[66]] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10 set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gp_out[66]] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,IO_L13_MRCC_12_JX3_N,P13,10
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS18} [get_ports gp_in[66]] ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9 set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gp_in[66]] ; ## U1,AB14,IO_L14_SRCC_12_JX3_N,JX3,94,IO_L14_SRCC_12_JX3_N,P13,9
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS18} [get_ports gp_out[67]] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12 set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports gp_out[67]] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,IO_L13_MRCC_12_JX3_P,P13,12
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18} [get_ports gp_in[67]] ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11 set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gp_in[67]] ; ## U1,AB15,IO_L14_SRCC_12_JX3_P,JX3,92,IO_L14_SRCC_12_JX3_P,P13,11
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports gp_out[68]] ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14 set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports gp_out[68]] ; ## U1,AD11,IO_L11_SRCC_12_JX3_N,JX3,87,IO_L11_SRCC_12_JX3_N,P13,14
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS18} [get_ports gp_in[68]] ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13 set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gp_in[68]] ; ## U1,AD13,IO_L12_MRCC_12_JX3_N,JX3,88,IO_L12_MRCC_12_JX3_N,P13,13
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports gp_out[69]] ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16 set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gp_out[69]] ; ## U1,AC12,IO_L11_SRCC_12_JX3_P,JX3,85,IO_L11_SRCC_12_JX3_P,P13,16
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS18} [get_ports gp_in[69]] ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15 set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports gp_in[69]] ; ## U1,AC13,IO_L12_MRCC_12_JX3_P,JX3,86,IO_L12_MRCC_12_JX3_P,P13,15
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS18} [get_ports gp_out[70]] ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20 set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports gp_out[70]] ; ## U1,AF10,IO_L09_12_JX3_N,JX3,81,IO_L09_12_JX3_N,P13,20
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports gp_in[70]] ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19 set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gp_in[70]] ; ## U1,AF13,IO_L10_12_JX3_N,JX3,82,IO_L10_12_JX3_N,P13,19
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports gp_out[71]] ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22 set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports gp_out[71]] ; ## U1,AE11,IO_L09_12_JX3_P,JX3,79,IO_L09_12_JX3_P,P13,22
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports gp_in[71]] ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21 set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gp_in[71]] ; ## U1,AE13,IO_L10_12_JX3_P,JX3,80,IO_L10_12_JX3_P,P13,21
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports gp_out[72]] ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24 set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports gp_out[72]] ; ## U1,AD10,IO_L07_12_JX3_N,JX3,75,IO_L07_12_JX3_N,P13,24
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports gp_in[72]] ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23 set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gp_in[72]] ; ## U1,AF12,IO_L08_12_JX3_N,JX3,76,IO_L08_12_JX3_N,P13,23
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gp_out[73]] ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26 set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports gp_out[73]] ; ## U1,AE10,IO_L07_12_JX3_P,JX3,73,IO_L07_12_JX3_P,P13,26
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports gp_in[73]] ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25 set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gp_in[73]] ; ## U1,AE12,IO_L08_12_JX3_P,JX3,74,IO_L08_12_JX3_P,P13,25
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS18} [get_ports gp_out[74]] ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28 set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports gp_out[74]] ; ## U1,Y13,IO_L05_12_JX3_N,JX3,44,IO_L05_12_JX3_N,P13,28
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports gp_in[74]] ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27 set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gp_in[74]] ; ## U1,AA12,IO_L06_12_JX3_N,JX3,66,IO_L06_12_JX3_N,P13,27
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS18} [get_ports gp_out[75]] ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30 set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports gp_out[75]] ; ## U1,W13,IO_L05_12_JX3_P,JX3,42,IO_L05_12_JX3_P,P13,30
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18} [get_ports gp_in[75]] ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29 set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports gp_in[75]] ; ## U1,AA13,IO_L06_12_JX3_P,JX3,64,IO_L06_12_JX3_P,P13,29
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports gp_out[76]] ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32 set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports gp_out[76]] ; ## U1,AA10,IO_L03_12_JX3_N,JX3,28,IO_L03_12_JX3_N,P13,32
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports gp_in[76]] ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31 set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports gp_in[76]] ; ## U1,AB10,IO_L04_12_JX3_N,JX3,33,IO_L04_12_JX3_N,P13,31
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports gp_out[77]] ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34 set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports gp_out[77]] ; ## U1,Y10,IO_L03_12_JX3_P,JX3,26,IO_L03_12_JX3_P,P13,34
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports gp_in[77]] ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33 set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports gp_in[77]] ; ## U1,AB11,IO_L04_12_JX3_P,JX3,31,IO_L04_12_JX3_P,P13,33
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS18} [get_ports gp_out[78]] ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36 set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports gp_out[78]] ; ## U1,Y11,IO_L01_12_JX3_N,JX3,22,IO_L01_12_JX3_N,P13,36
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports gp_in[78]] ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35 set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports gp_in[78]] ; ## U1,AC11,IO_L02_12_JX3_N,JX3,27,IO_L02_12_JX3_N,P13,35
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports gp_out[79]] ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38 set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports gp_out[79]] ; ## U1,Y12,IO_L01_12_JX3_P,JX3,20,IO_L01_12_JX3_P,P13,38
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gp_in[79]] ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37 set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gp_in[79]] ; ## U1,AB12,IO_L02_12_JX3_P,JX3,25,IO_L02_12_JX3_P,P13,37
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS18} [get_ports gp_out[80]] ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42 set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports gp_out[80]] ; ## U1,AE16,IO_L17_12_JX2_P,JX2,82,IO_L17_12_JX2_P,P13,42
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS18} [get_ports gp_in[80]] ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41 set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gp_in[80]] ; ## U1,AE17,IO_L18_12_JX2_P,JX2,81,IO_L18_12_JX2_P,P13,41
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS18} [get_ports gp_out[81]] ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44 set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gp_out[81]] ; ## U1,AE15,IO_L17_12_JX2_N,JX2,84,IO_L17_12_JX2_N,P13,44
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS18} [get_ports gp_in[81]] ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43 set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports gp_in[81]] ; ## U1,AF17,IO_L18_12_JX2_N,JX2,83,IO_L18_12_JX2_N,P13,43
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports gp_out[82]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46 set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gp_out[82]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,IO_L19_12_JX2_P,P13,46
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports gp_in[82]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45 set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gp_in[82]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,IO_L20_12_JX2_P,P13,45
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS18} [get_ports gp_out[83]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48 set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gp_out[83]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,IO_L19_12_JX2_N,P13,48
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18} [get_ports gp_in[83]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47 set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gp_in[83]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,IO_L20_12_JX2_N,P13,47
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS18} [get_ports gp_out[84]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50 set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gp_out[84]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,IO_L21_12_JX2_P,P13,50
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS18} [get_ports gp_in[84]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49 set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_in[84]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,IO_L22_12_JX2_P,P13,49
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS18} [get_ports gp_out[85]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52 set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gp_out[85]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,IO_L21_12_JX2_N,P13,52
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports gp_in[85]] ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51 set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gp_in[85]] ; ## U1,AA14,IO_L22_12_JX2_N,JX2,96,IO_L22_12_JX2_N,P13,51
## transceiver loop-backs (on-ccbrk) ## transceiver loop-backs (on-ccbrk)

26
projects/pzsdr2/common/ccfmc_bd.tcl
View File

@ -142,14 +142,14 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb] set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb
create_bd_port -dir I gt_ref_clk create_bd_port -dir I gt_ref_clk_0
create_bd_port -dir I -from 1 -to 0 gt_rx_p create_bd_port -dir I -from 1 -to 0 gt_rx_p
create_bd_port -dir I -from 1 -to 0 gt_rx_n create_bd_port -dir I -from 1 -to 0 gt_rx_n
create_bd_port -dir O -from 1 -to 0 gt_tx_p create_bd_port -dir O -from 1 -to 0 gt_tx_p
create_bd_port -dir O -from 1 -to 0 gt_tx_n create_bd_port -dir O -from 1 -to 0 gt_tx_n
ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk_0
ad_connect axi_pz_xcvrlb/rx_p gt_rx_p ad_connect axi_pz_xcvrlb/rx_p gt_rx_p
ad_connect axi_pz_xcvrlb/rx_n gt_rx_n ad_connect axi_pz_xcvrlb/rx_n gt_rx_n
ad_connect axi_pz_xcvrlb/tx_p gt_tx_p ad_connect axi_pz_xcvrlb/tx_p gt_tx_p
@ -159,42 +159,26 @@ ad_connect axi_pz_xcvrlb/tx_n gt_tx_n
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg
set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg
create_bd_port -dir I -from 31 -to 0 gp_in_0 create_bd_port -dir I -from 31 -to 0 gp_in_0
create_bd_port -dir I -from 31 -to 0 gp_in_1 create_bd_port -dir I -from 31 -to 0 gp_in_1
create_bd_port -dir I -from 31 -to 0 gp_in_2
create_bd_port -dir I -from 31 -to 0 gp_in_3
create_bd_port -dir O -from 31 -to 0 gp_out_0 create_bd_port -dir O -from 31 -to 0 gp_out_0
create_bd_port -dir O -from 31 -to 0 gp_out_1 create_bd_port -dir O -from 31 -to 0 gp_out_1
create_bd_port -dir O -from 31 -to 0 gp_out_2
create_bd_port -dir O -from 31 -to 0 gp_out_3
create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
create_bd_port -dir O -from 31 -to 0 gp_ioenb_2
create_bd_port -dir O -from 31 -to 0 gp_ioenb_3
create_bd_port -dir I clk_0 create_bd_port -dir I clk_0
create_bd_port -dir I clk_1 create_bd_port -dir I clk_1
create_bd_port -dir I clk_2 create_bd_port -dir I gt_ref_clk_1
ad_connect clk_0 axi_gpreg/d_clk_0 ad_connect clk_0 axi_gpreg/d_clk_0
ad_connect clk_1 axi_gpreg/d_clk_1 ad_connect clk_1 axi_gpreg/d_clk_1
ad_connect clk_2 axi_gpreg/d_clk_2 ad_connect gt_ref_clk_1 axi_gpreg/d_clk_2
ad_connect gp_in_0 axi_gpreg/up_gp_in_0 ad_connect gp_in_0 axi_gpreg/up_gp_in_0
ad_connect gp_in_1 axi_gpreg/up_gp_in_1 ad_connect gp_in_1 axi_gpreg/up_gp_in_1
ad_connect gp_in_2 axi_gpreg/up_gp_in_2
ad_connect gp_in_3 axi_gpreg/up_gp_in_3
ad_connect gp_out_0 axi_gpreg/up_gp_out_0 ad_connect gp_out_0 axi_gpreg/up_gp_out_0
ad_connect gp_out_1 axi_gpreg/up_gp_out_1 ad_connect gp_out_1 axi_gpreg/up_gp_out_1
ad_connect gp_out_2 axi_gpreg/up_gp_out_2
ad_connect gp_out_3 axi_gpreg/up_gp_out_3
ad_connect gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
ad_connect gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
ad_connect gp_ioenb_2 axi_gpreg/up_gp_ioenb_2
ad_connect gp_ioenb_3 axi_gpreg/up_gp_ioenb_3
ad_cpu_interconnect 0x41200000 axi_gpreg ad_cpu_interconnect 0x41200000 axi_gpreg
## temporary (remove ila indirectly) ## temporary (remove ila indirectly)

62
projects/pzsdr2/common/pzsdr2_bd.tcl
View File

@ -362,4 +362,66 @@ set_property CONFIG.DAC_USERPORTS_DISABLE 0 [get_bd_cells axi_ad9361]
set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361] set_property CONFIG.TDD_DISABLE 0 [get_bd_cells axi_ad9361]
## lvds/cmos configuration
## core digital interface -- cmos (1) or lvds (0)
proc cfg_ad9361_interface {cmos_or_lvds} {
if {$cmos_or_lvds eq "LVDS"} {
set_property CONFIG.CMOS_OR_LVDS_N 0 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in_p
create_bd_port -dir I rx_clk_in_n
create_bd_port -dir I rx_frame_in_p
create_bd_port -dir I rx_frame_in_n
create_bd_port -dir I -from 5 -to 0 rx_data_in_p
create_bd_port -dir I -from 5 -to 0 rx_data_in_n
create_bd_port -dir O tx_clk_out_p
create_bd_port -dir O tx_clk_out_n
create_bd_port -dir O tx_frame_out_p
create_bd_port -dir O tx_frame_out_n
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
return
}
if {$cmos_or_lvds eq "CMOS"} {
set_property CONFIG.CMOS_OR_LVDS_N 1 [get_bd_cells axi_ad9361]
create_bd_port -dir I rx_clk_in
create_bd_port -dir I rx_frame_in
create_bd_port -dir I -from 11 -to 0 rx_data_in
create_bd_port -dir O tx_clk_out
create_bd_port -dir O tx_frame_out
create_bd_port -dir O -from 11 -to 0 tx_data_out
ad_connect rx_clk_in axi_ad9361/rx_clk_in
ad_connect rx_frame_in axi_ad9361/rx_frame_in
ad_connect rx_data_in axi_ad9361/rx_data_in
ad_connect tx_clk_out axi_ad9361/tx_clk_out
ad_connect tx_frame_out axi_ad9361/tx_frame_out
ad_connect tx_data_out axi_ad9361/tx_data_out
return
}
}

4
projects/pzsdr2/common/pzsdr2_constr.xdc
View File

@ -31,8 +31,8 @@ set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports clkout_in
# iic (ccbrk with loopback drives i2c back to the FPGA) # iic (ccbrk with loopback drives i2c back to the FPGA)
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4 set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13 U1,AF24,SCL,JX2,17,I2C_SCL,P2,14,P2,4,U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3,P2,4
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15 set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13 U1,AF25,SDA,JX2,19,I2C_SDA,P2,16,P2,15,U1,AB24,IO_L06_13_JX2_N,JX2,20,IO_L06_13_JX2_N,P2,15
## reference-only ## reference-only
## -------------- ## --------------