From fb269f7a2910d074b3592453089995ac75b28e6c Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 24 Nov 2015 11:18:18 +0200 Subject: [PATCH] util_cpack: Updated altera interfaces - DMA side, simplified naming - ADC side, added FIFO conduit per channel --- library/util_cpack/util_cpack_hw.tcl | 73 +++++++++++++++++----------- 1 file changed, 45 insertions(+), 28 deletions(-) diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl index b2a3d1c6a..889704d3c 100755 --- a/library/util_cpack/util_cpack_hw.tcl +++ b/library/util_cpack/util_cpack_hw.tcl @@ -39,50 +39,67 @@ set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true # defaults ad_alt_intf clock adc_clk input 1 -ad_alt_intf reset adc_rst input 1 if_adc_clk -ad_alt_intf signal adc_valid output 1 -ad_alt_intf signal adc_sync output 1 -ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH -ad_alt_intf signal adc_valid_0 input 1 -ad_alt_intf signal adc_enable_0 input 1 -ad_alt_intf signal adc_data_0 input CHANNEL_DATA_WIDTH +ad_alt_intf reset adc_rst input 1 if_adc_clk +ad_alt_intf signal adc_valid output 1 valid +ad_alt_intf signal adc_sync output 1 sync +ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data + +add_interface fifo_ch_0 conduit end +#set_interface_property fifo_ch_0 associatedClock if_adc_clk +add_interface_port fifo_ch_0 adc_enable_0 enable Input 1 +add_interface_port fifo_ch_0 adc_valid_0 valid Input 1 +add_interface_port fifo_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH proc p_util_cpack {} { if {[get_parameter_value NUM_OF_CHANNELS] > 1} { - ad_alt_intf signal adc_valid_1 input 1 - ad_alt_intf signal adc_enable_1 input 1 - ad_alt_intf signal adc_data_1 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_1 conduit end + #set_interface_property fifo_ch_1 associatedClock if_adc_clk + add_interface_port fifo_ch_1 adc_enable_1 enable Input 1 + add_interface_port fifo_ch_1 adc_valid_1 valid Input 1 + add_interface_port fifo_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 2} { - ad_alt_intf signal adc_valid_2 input 1 - ad_alt_intf signal adc_enable_2 input 1 - ad_alt_intf signal adc_data_2 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_2 conduit end + #set_interface_property fifo_ch_2 associatedClock if_adc_clk + add_interface_port fifo_ch_2 adc_enable_2 enable Input 1 + add_interface_port fifo_ch_2 adc_valid_2 valid Input 1 + add_interface_port fifo_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 3} { - ad_alt_intf signal adc_valid_3 input 1 - ad_alt_intf signal adc_enable_3 input 1 - ad_alt_intf signal adc_data_3 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_3 conduit end + #set_interface_property fifo_ch_3 associatedClock if_adc_clk + add_interface_port fifo_ch_3 adc_enable_3 enable Input 1 + add_interface_port fifo_ch_3 adc_valid_3 valid Input 1 + add_interface_port fifo_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 4} { - ad_alt_intf signal adc_valid_4 input 1 - ad_alt_intf signal adc_enable_4 input 1 - ad_alt_intf signal adc_data_4 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_4 conduit end + #set_interface_property fifo_ch_4 associatedClock if_adc_clk + add_interface_port fifo_ch_4 adc_enable_4 enable Input 1 + add_interface_port fifo_ch_4 adc_valid_4 valid Input 1 + add_interface_port fifo_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 5} { - ad_alt_intf signal adc_valid_5 input 1 - ad_alt_intf signal adc_enable_5 input 1 - ad_alt_intf signal adc_data_5 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_5 conduit end + #set_interface_property fifo_ch_5 associatedClock if_adc_clk + add_interface_port fifo_ch_5 adc_enable_5 enable Input 1 + add_interface_port fifo_ch_5 adc_valid_5 valid Input 1 + add_interface_port fifo_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 6} { - ad_alt_intf signal adc_valid_6 input 1 - ad_alt_intf signal adc_enable_6 input 1 - ad_alt_intf signal adc_data_6 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_6 conduit end + #set_interface_property fifo_ch_6 associatedClock if_adc_clk + add_interface_port fifo_ch_6 adc_enable_6 enable Input 1 + add_interface_port fifo_ch_6 adc_valid_6 valid Input 1 + add_interface_port fifo_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH } if {[get_parameter_value NUM_OF_CHANNELS] > 7} { - ad_alt_intf signal adc_valid_7 input 1 - ad_alt_intf signal adc_enable_7 input 1 - ad_alt_intf signal adc_data_7 input CHANNEL_DATA_WIDTH + add_interface fifo_ch_7 conduit end + #set_interface_property fifo_ch_7 associatedClock if_adc_clk + add_interface_port fifo_ch_7 adc_enable_7 enable Input 1 + add_interface_port fifo_ch_7 adc_valid_7 valid Input 1 + add_interface_port fifo_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH } }