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ad_csc: Generalize for CrYCB 2 RGB conversion

main
AndreiGrozav 2018-09-18 16:30:50 +03:00 committed by AndreiGrozav
parent 74eacc2369
commit fae4d478d4
4 changed files with 71 additions and 37 deletions
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4
library/axi_hdmi_rx/Makefile
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@ -5,9 +5,7 @@
LIBRARY_NAME := axi_hdmi_rx
GENERIC_DEPS += ../common/ad_csc_1.v
GENERIC_DEPS += ../common/ad_csc_1_add.v
GENERIC_DEPS += ../common/ad_csc_1_mul.v
GENERIC_DEPS += ../common/ad_csc.v
GENERIC_DEPS += ../common/ad_csc_CrYCb2RGB.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/ad_ss_422to444.v

4
library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
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@ -10,9 +10,7 @@ adi_ip_files axi_hdmi_rx [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_csc_1.v" \
"$ad_hdl_dir/library/common/ad_csc_1_mul.v" \
"$ad_hdl_dir/library/common/ad_csc_1_add.v" \
"$ad_hdl_dir/library/common/ad_csc.v" \
"$ad_hdl_dir/library/common/ad_ss_422to444.v" \
"$ad_hdl_dir/library/common/ad_csc_CrYCb2RGB.v" \
"$ad_hdl_dir/library/common/up_axi.v" \

37
library/common/ad_csc.v
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@ -38,7 +38,10 @@
module ad_csc #(
parameter DELAY_DW = 16) (
parameter DELAY_DW = 16,
parameter MUL_COEF_DW = 17,
parameter SUM_COEF_DW = 24,
parameter YCbCr_2_RGB = 0) (
// data
@ -48,10 +51,10 @@ module ad_csc #(
// constants
input signed [16:0] C1,
input signed [16:0] C2,
input signed [16:0] C3,
input signed [23:0] C4,
input signed [MUL_COEF_DW-1:0] C1,
input signed [MUL_COEF_DW-1:0] C2,
input signed [MUL_COEF_DW-1:0] C3,
input signed [SUM_COEF_DW-1:0] C4,
// sync is delay matched
@ -76,6 +79,7 @@ module ad_csc #(
reg [DELAY_DW-1:0] sync_2_m;
reg [DELAY_DW-1:0] sync_3_m;
reg [DELAY_DW-1:0] sync_4_m;
reg [DELAY_DW-1:0] sync_5_m;
reg [ 7:0] csc_data_d;
@ -92,7 +96,7 @@ module ad_csc #(
sync_2_m <= sync_1_m;
sync_3_m <= sync_2_m;
sync_4_m <= sync_3_m;
csc_sync <= sync_4_m;
sync_5_m <= sync_4_m;
end
assign color1 = {1'd0, data[23:16]};
@ -113,7 +117,28 @@ module ad_csc #(
s_data_3 <= s_data_2 + data_3;
end
generate
// in RGB to YCbCr there are no overflows or underflows
if (YCbCr_2_RGB) begin
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
if (s_data_3[27] == 1'b1) begin
csc_data_d <= 8'h0;
end else if (s_data_3[26:24] != 3'b0) begin
csc_data_d <= 8'hff;
end else begin
csc_data_d <= s_data_3[22:15];
end
end
assign csc_data = csc_data_d;
assign csc_sync = sync_5_m;
end else begin
assign csc_data = s_data_3[23:16];
assign csc_sync = sync_4_m;
end
endgenerate
endmodule

55
library/common/ad_csc_CrYCb2RGB.v
View File

@ -60,42 +60,55 @@ module ad_csc_CrYCb2RGB #(
// red
ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_R (
ad_csc #(
.DELAY_DW (DELAY_DATA_WIDTH),
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_R (
.clk (clk),
.sync (CrYCb_sync),
.data (CrYCb_data),
.C1 (17'h01989),
.C2 (17'h012a1),
.C3 (17'h00000),
.C4 (25'h10deebc),
.csc_sync_1 (RGB_sync),
.csc_data_1 (RGB_data[23:16]));
.C1 ( 18'd52299),
.C2 ( 18'd38154),
.C3 ( 18'd0),
.C4 (-28'd7304675),
.csc_sync (RGB_sync),
.csc_data (RGB_data[23:16]));
// green
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_G (
ad_csc #(
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_G (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h10d01),
.C2 (17'h012a1),
.C3 (17'h10644),
.C4 (25'h0087937),
.csc_sync_1 (),
.csc_data_1 (RGB_data[15:8]));
.C1 (-18'd26639),
.C2 ( 18'd38154),
.C3 (-18'd12837),
.C4 ( 28'd4442554),
.csc_sync (),
.csc_data (RGB_data[15:8]));
// blue
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_B (
ad_csc #(
.MUL_COEF_DW (18),
.SUM_COEF_DW (28),
.YCbCr_2_RGB (1))
i_csc_B (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h00000),
.C2 (17'h012a1),
.C3 (17'h02046),
.C4 (25'h1114d60),
.csc_sync_1 (),
.csc_data_1 (RGB_data[7:0]));
.C1 ( 18'd0),
.C2 ( 18'd38154),
.C3 ( 18'd66101),
.C4 (-28'd9071362),
.csc_sync (),
.csc_data (RGB_data[7:0]));
endmodule