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util_dacfifo: Fix the reset logic of the module 

Both the DMA and DAC side should be in reset at the positive edge of the
dma_xfer_req, so we can re-initialize the buffer.
main
Istvan Csomortani 2018-08-22 13:05:00 +01:00 committed by István Csomortáni
parent 6044aa3956
commit fa32ea8f1f
4 changed files with 61 additions and 10 deletions
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62
library/util_dacfifo/util_dacfifo.v
View File

@ -66,6 +66,7 @@ module util_dacfifo #(
// internal registers
reg dma_init = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_waddr_g = 'b0;
reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_g = 'b0;
@ -76,6 +77,8 @@ module util_dacfifo #(
reg dma_ready_fifo = 1'b0;
reg dma_bypass = 1'b0;
reg dma_bypass_m1 = 1'b0;
reg dma_xfer_req_d1 = 1'b0;
reg dma_xfer_req_d2 = 1'b0;
reg dma_xfer_out_fifo = 1'b0;
reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0;
@ -88,6 +91,9 @@ module util_dacfifo #(
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0;
reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0;
reg dac_mem_ready = 1'b0;
reg dac_xfer_req_m1 = 1'b0;
reg dac_xfer_req = 1'b0;
reg dac_xfer_req_d = 1'b0;
reg dac_xfer_out_fifo = 1'b0;
reg dac_xfer_out_fifo_m1 = 1'b0;
reg dac_xfer_out_fifo_d = 1'b0;
@ -96,7 +102,9 @@ module util_dacfifo #(
// internal wires
wire dma_rst_int_s;
wire dma_wren_s;
wire dma_xfer_posedge_s;
wire dma_ready_bypass_s;
wire [(DATA_WIDTH-1):0] dac_data_fifo_s;
wire [(DATA_WIDTH-1):0] dac_data_bypass_s;
@ -108,13 +116,41 @@ module util_dacfifo #(
wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s;
wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s;
wire dac_mem_ren_s;
wire dac_xfer_posedge_s;
wire dac_rst_int_s;
// internal reset generation
always @(posedge dma_clk) begin
dma_xfer_req_d1 <= dma_xfer_req;
dma_xfer_req_d2 <= dma_xfer_req_d1;
end
assign dma_xfer_posedge_s = ~dma_xfer_req_d2 & dma_xfer_req_d1;
// status register indicating that the module is in initialization phase
always @(posedge dma_clk) begin
if ((dma_rst == 1'b1) || (dma_xfer_last == 1'b1)) begin
dma_init <= 1'b0;
end else begin
if (dma_xfer_posedge_s == 1'b1) begin
dma_init <= 1'b1;
end
end
end
// if the module is not in initialization phase, it should go
// into reset at a positive edge of dma_xfer_req
assign dma_rst_int_s = dma_rst | (dma_xfer_posedge_s & ~dma_init);
// DMA / Write interface
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
if (dma_rst_int_s == 1'b1) begin
dma_addr_diff <= 'b0;
dma_raddr_m1 <= 'b0;
dma_raddr_m2 <= 'b0;
@ -144,7 +180,7 @@ module util_dacfifo #(
assign dma_wren_s = dma_valid & dma_ready;
always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin
if(dma_rst_int_s == 1'b1) begin
dma_waddr <= 'b0;
dma_waddr_g <= 'b0;
dma_xfer_out_fifo <= 1'b0;
@ -169,7 +205,7 @@ module util_dacfifo #(
// save the last write address
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
if (dma_rst_int_s == 1'b1) begin
dma_lastaddr_g <= 'b0;
end else begin
if (dma_bypass == 1'b0) begin
@ -180,12 +216,22 @@ module util_dacfifo #(
// DAC / Read interface
// The memory module is ready if it's not empty
always @(posedge dac_clk) begin
dac_xfer_req_m1 <= dma_xfer_req;
dac_xfer_req <= dac_xfer_req_m1;
dac_xfer_req_d <= dac_xfer_req;
end
assign dac_xfer_posedge_s = ~dac_xfer_req_d & dac_xfer_req;
// we can reset the DAC side at each positive edge of xfer_req, even if
// sometimes the reset is redundant
assign dac_rst_int_s = dac_xfer_posedge_s | dac_rst;
assign dac_addr_diff_s = {1'b1, dac_waddr} - dac_raddr;
// The memory module is ready if it's not empty
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
if (dac_rst_int_s == 1'b1) begin
dac_addr_diff <= 'b0;
dac_waddr_m1 <= 'b0;
dac_waddr_m2 <= 'b0;
@ -213,7 +259,7 @@ module util_dacfifo #(
// sync lastaddr to dac clock domain
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
if (dac_rst_int_s == 1'b1) begin
dac_lastaddr_m1 <= 1'b0;
dac_lastaddr_m2 <= 1'b0;
dac_xfer_out_fifo_m1 <= 1'b0;
@ -241,7 +287,7 @@ module util_dacfifo #(
(dac_valid & dac_xfer_out_fifo);
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
if (dac_rst_int_s == 1'b1) begin
dac_raddr <= 'b0;
dac_raddr_g <= 'b0;
end else begin
@ -281,7 +327,7 @@ module util_dacfifo #(
// underflow make sense just if bypass is enabled
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
if (dac_rst_int_s == 1'b1) begin
dac_dunf <= 1'b0;
end else begin
dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_req & ~dac_mem_ren_s) : 1'b0;

3
library/util_dacfifo/util_dacfifo_constr.sdc
View File

@ -6,9 +6,10 @@ set_false_path -from [get_registers *dac_raddr_g*] -to [get_registers *dma_raddr
set_false_path -from [get_registers *dma_waddr_g*] -to [get_registers *dac_waddr_m1*]
set_false_path -from [get_registers *dma_lastaddr_g*] -to [get_registers *dac_lastaddr_m1*]
set_false_path -from [get_registers *dma_xfer_out_fifo*] -to [get_registers *dac_xfer_out_fifo_m1*]
set_false_path -from [get_registers *dma_xfer_out_bypass*] -to [get_registers *dac_xfer_out_bypass_m1*]
set_false_path -from [get_registers *dma_mem_waddr_g*] -to [get_registers *dac_mem_waddr_m1*]
set_false_path -from [get_registers *dac_mem_raddr_g*] -to [get_registers *dma_mem_raddr_m1*]
set_false_path -to [get_registers *dma_rst_m1*]
set_false_path -to [get_registers *dac_xfer_req_m1*]

4
library/util_dacfifo/util_dacfifo_constr.xdc
View File

@ -4,7 +4,8 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_raddr_m*}] \
[get_cells -hier -filter {name =~ *dac_lastaddr_m*}] \
[get_cells -hier -filter {name =~ *dac_xfer_out_*}] \
[get_cells -hier -filter {name =~ *dma_bypass*}] \
[get_cells -hier -filter {name =~ *dac_bypass*}]
[get_cells -hier -filter {name =~ *dac_bypass*}] \
[get_cells -hier -filter {name =~ *dac_xfer_req_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *dac_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_raddr_m1* && IS_SEQUENTIAL}]
@ -29,4 +30,5 @@ set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS
set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ */dac_xfer_req_m1_reg && IS_SEQUENTIAL}]

2
library/util_dacfifo/util_dacfifo_hw.tcl
View File

@ -6,9 +6,11 @@ source ../scripts/adi_ip_alt.tcl
ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
ad_ip_files util_dacfifo [list\
$ad_hdl_dir/library/common/ad_mem.v \
$ad_hdl_dir/library/common/ad_mem_asym.v \
$ad_hdl_dir/library/common/ad_b2g.v \
$ad_hdl_dir/library/common/ad_g2b.v \
util_dacfifo.v \
util_dacfifo_bypass.v \
util_dacfifo_constr.sdc]
# parameters