From f9ca4fb8be8e170376ecee5754ae15cd74e6e5e2 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 7 Apr 2014 10:58:17 +0200 Subject: [PATCH] axi_fifo: Slightly improve timing It is OK to overwrite invalid data with other invalid data. Signed-off-by: Lars-Peter Clausen --- library/axi_fifo/axi_fifo.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/library/axi_fifo/axi_fifo.v b/library/axi_fifo/axi_fifo.v index 4c8a6bab3..16e67788a 100644 --- a/library/axi_fifo/axi_fifo.v +++ b/library/axi_fifo/axi_fifo.v @@ -88,13 +88,17 @@ assign m_axis_valid = m_axis_raddr != m_axis_waddr; assign s_axis_ready = s_axis_raddr == s_axis_waddr; assign s_axis_empty = s_axis_raddr == s_axis_waddr; +always @(posedge s_axis_aclk) begin + if (s_axis_ready) + ram <= s_axis_data; +end + always @(posedge s_axis_aclk) begin if (s_axis_aresetn == 1'b0) begin s_axis_waddr <= 1'b0; end else begin if (s_axis_ready & s_axis_valid) begin s_axis_waddr <= s_axis_waddr + 1'b1; - ram <= s_axis_data; end end end @@ -179,7 +183,7 @@ always @(posedge m_axis_aclk) begin end always @(posedge m_axis_aclk) begin - if ((~valid || m_axis_ready) && _m_axis_valid) + if (~valid || m_axis_ready) data <= ram[m_axis_raddr]; end