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adrv9371x- added

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Rejeesh Kutty 2016-05-20 11:46:25 -04:00
parent b5b05bb9d1
commit f92e8509bb
10 changed files with 1977 additions and 0 deletions
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142
projects/adrv9371x/a10soc/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += system_bd.qsys
M_DEPS += ../common/fmcomms2_bd.qsys
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_addsub.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dcfilter.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_iqcor.v
M_DEPS += ../../../library/common/ad_mul.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_tdd_control.v
M_DEPS += ../../../library/common/altera/DSP48E1.v
M_DEPS += ../../../library/common/altera/MULT_MACRO.v
M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
M_DEPS += ../../../library/common/altera/ad_cmos_in.v
M_DEPS += ../../../library/common/altera/ad_cmos_out.v
M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
M_DEPS += ../../../library/common/altera/ad_lvds_in.v
M_DEPS += ../../../library/common/altera/ad_lvds_out.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_tdd_cntrl.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
.PHONY: all clean clean-all
all: fmcomms2_a10soc.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
fmcomms2_a10soc.sof: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> fmcomms2_a10soc_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/adrv9371x/a10soc/system_bd.qsys Executable file
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element a10soc
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element a10soc.hps_s1_axi
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element fmcomms2
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element fmcomms2.axi_ad9361_s_axi
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element fmcomms2.axi_dmac_adc_s_axi
{
datum baseAddress
{
value = "81920";
type = "String";
}
}
element fmcomms2.axi_dmac_dac_s_axi
{
datum baseAddress
{
value = "65536";
type = "String";
}
}
element sys_clk
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="10AS066N3F40E2SGE2" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="2" />
<parameter name="projectName" value="fmcomms2_a10soc.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="ad9361_if"
internal="fmcomms2.axi_ad9361_device_if"
type="conduit"
dir="end" />
<interface
name="delay_clk"
internal="fmcomms2.axi_ad9361_delay_clk"
type="clock"
dir="end" />
<interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
<interface
name="hps_ddr_oct"
internal="a10soc.hps_ddr_oct"
type="conduit"
dir="end" />
<interface
name="hps_ddr_ref_clk"
internal="a10soc.hps_ddr_ref_clk"
type="clock"
dir="end" />
<interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
<interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
<interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
<interface
name="hps_spi0_sclk"
internal="a10soc.hps_spi0_sclk"
type="clock"
dir="start" />
<interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
<interface
name="hps_spi1_sclk"
internal="a10soc.hps_spi1_sclk"
type="clock"
dir="start" />
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
<interface
name="sys_reset"
internal="sys_clk.clk_in_reset"
type="reset"
dir="end" />
<interface
name="up_enable"
internal="fmcomms2.axi_ad9361_up_enable"
type="conduit"
dir="end" />
<interface
name="up_txnrx"
internal="fmcomms2.axi_ad9361_up_txnrx"
type="conduit"
dir="end" />
<module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
<parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
<parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
<parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
</module>
<module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
value="AddressWidth = 32" />
<parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
value="AddressWidth = 32" />
<parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
</module>
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<connection
kind="avalon"
version="15.1"
start="fmcomms2.axi_dmac_adc_m_dest_axi"
end="a10soc.hps_s1_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="fmcomms2.axi_dmac_dac_m_src_axi"
end="a10soc.hps_s1_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_ad9361_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_dmac_adc_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00014000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_dmac_dac_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
<connection
kind="clock"
version="15.1"
start="sys_clk.clk"
end="fmcomms2.sys_clk" />
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq0"
end="fmcomms2.axi_dmac_adc_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq0"
end="fmcomms2.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq1"
end="fmcomms2.axi_dmac_adc_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq1"
end="fmcomms2.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="reset"
version="15.1"
start="sys_clk.clk_reset"
end="a10soc.sys_rst_in" />
<connection
kind="reset"
version="15.1"
start="a10soc.sys_rst"
end="fmcomms2.sys_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
</system>

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projects/adrv9371x/a10soc/system_constr.sdc Normal file
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk_in}]
derive_pll_clocks
derive_clock_uncertainty

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projects/adrv9371x/a10soc/system_project.tcl Normal file
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load_package flow
source ../../scripts/adi_env.tcl
project_new fmcomms2_a10soc -overwrite
source "../../common/a10soc/a10soc_system_assign.tcl"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# ad9371
set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_location_assignment PIN_R32 -to rx_data[0] ; ## A02 FMC_HPC_DP1_M2C_P
set_location_assignment PIN_R33 -to "rx_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N
set_location_assignment PIN_P34 -to rx_data[1] ; ## A06 FMC_HPC_DP2_M2C_P
set_location_assignment PIN_P35 -to "rx_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N
set_location_assignment PIN_T30 -to rx_data[2] ; ## C06 FMC_HPC_DP0_M2C_P
set_location_assignment PIN_T31 -to "rx_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N
set_location_assignment PIN_P30 -to rx_data[3] ; ## A10 FMC_HPC_DP3_M2C_P
set_location_assignment PIN_P31 -to "rx_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N
set_location_assignment PIN_M38 -to tx_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3])
set_location_assignment PIN_M39 -to "tx_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3])
set_location_assignment PIN_L36 -to tx_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0])
set_location_assignment PIN_L37 -to "tx_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0])
set_location_assignment PIN_N36 -to tx_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1])
set_location_assignment PIN_N37 -to "tx_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1])
set_location_assignment PIN_K38 -to tx_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2])
set_location_assignment PIN_K39 -to "tx_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2])
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
set_location_assignment PIN_C14 -to rx_sync ; ## G09 FMC_HPC_LA03_P
set_location_assignment PIN_D14 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N
set_location_assignment PIN_E3 -to rx_os_sync ; ## G27 FMC_HPC_LA25_P (Sniffer)
set_location_assignment PIN_F3 -to rx_os_sync(n) ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_location_assignment PIN_C13 -to tx_sync ; ## H07 FMC_HPC_LA02_P
set_location_assignment PIN_D13 -to tx_sync(n) ; ## H08 FMC_HPC_LA02_N
set_location_assignment PIN_P11 -to sysref ; ## G36 FMC_HPC_LA33_P
set_location_assignment PIN_R11 -to sysref(n) ; ## G37 FMC_HPC_LA33_N
set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync
set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
set_instance_assignment -name IO_STANDARD LVDS -to sysref
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
set_location_assignment PIN_A12 -to spi_csn_ad9528 ; ## D15 FMC_HPC_LA09_N
set_location_assignment PIN_A13 -to spi_csn_ad9371 ; ## D14 FMC_HPC_LA09_P
set_location_assignment PIN_A9 -to spi_clk ; ## H13 FMC_HPC_LA07_P
set_location_assignment PIN_B9 -to spi_mosi ; ## H14 FMC_HPC_LA07_N
set_location_assignment PIN_B11 -to spi_miso ; ## G12 FMC_HPC_LA08_P
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
set_location_assignment PIN_F2 -to ad9528_reset_b ; ## D26 FMC_HPC_LA26_P
set_location_assignment PIN_G2 -to ad9528_sysref_req ; ## D27 FMC_HPC_LA26_N
set_location_assignment PIN_J11 -to ad9371_tx1_enable ; ## D17 FMC_HPC_LA13_P
set_location_assignment PIN_J9 -to ad9371_tx2_enable ; ## C18 FMC_HPC_LA14_P
set_location_assignment PIN_K11 -to ad9371_rx1_enable ; ## D18 FMC_HPC_LA13_N
set_location_assignment PIN_J10 -to ad9371_rx2_enable ; ## C19 FMC_HPC_LA14_N
set_location_assignment PIN_F13 -to ad9371_test ; ## D11 FMC_HPC_LA05_P (DNI/NC)
set_location_assignment PIN_H12 -to ad9371_reset_b ; ## H10 FMC_HPC_LA04_P
set_location_assignment PIN_H13 -to ad9371_gpint ; ## H11 FMC_HPC_LA04_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint
set_location_assignment PIN_D4 -to ad9371_gpio_00 ; ## H19 FMC_HPC_LA15_P
set_location_assignment PIN_D5 -to ad9371_gpio_01 ; ## H20 FMC_HPC_LA15_N
set_location_assignment PIN_D6 -to ad9371_gpio_02 ; ## G18 FMC_HPC_LA16_P
set_location_assignment PIN_E6 -to ad9371_gpio_03 ; ## G19 FMC_HPC_LA16_N
set_location_assignment PIN_C2 -to ad9371_gpio_04 ; ## H25 FMC_HPC_LA21_P
set_location_assignment PIN_D3 -to ad9371_gpio_05 ; ## H26 FMC_HPC_LA21_N
set_location_assignment PIN_G7 -to ad9371_gpio_06 ; ## C22 FMC_HPC_LA18_CC_P
set_location_assignment PIN_H7 -to ad9371_gpio_07 ; ## C23 FMC_HPC_LA18_CC_N
set_location_assignment PIN_F4 -to ad9371_gpio_15 ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_location_assignment PIN_G4 -to ad9371_gpio_08 ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
set_location_assignment PIN_G5 -to ad9371_gpio_09 ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
set_location_assignment PIN_G6 -to ad9371_gpio_10 ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_location_assignment PIN_C3 -to ad9371_gpio_11 ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_location_assignment PIN_C4 -to ad9371_gpio_12 ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_location_assignment PIN_N9 -to ad9371_gpio_14 ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
set_location_assignment PIN_P10 -to ad9371_gpio_13 ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
set_location_assignment PIN_M12 -to ad9371_gpio_17 ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?)
set_location_assignment PIN_N13 -to ad9371_gpio_16 ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?)
set_location_assignment PIN_F14 -to ad9371_gpio_18 ; ## D12 FMC_HPC_LA05_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_00
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_01
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_02
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_03
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_04
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_05
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_06
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_07
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_15
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_08
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_09
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_10
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_11
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_12
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_14
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_13
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_17
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_16
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio_18
execute_flow -compile

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// hps-ddr4 (32)
input hps_ddr_ref_clk,
output [ 0:0] hps_ddr_clk_p,
output [ 0:0] hps_ddr_clk_n,
output [ 16:0] hsp_ddr_a,
output [ 1:0] hps_ddr_ba,
output [ 0:0] hps_ddr_bg,
output [ 0:0] hps_ddr_cke,
output [ 0:0] hps_ddr_cs_n,
output [ 0:0] hps_ddr_odt,
output [ 0:0] hps_ddr_reset_n,
output [ 0:0] hps_ddr_act_n,
output [ 0:0] hps_ddr_par,
input [ 0:0] hps_ddr_alert_n,
inout [ 3:0] hps_ddr_dqs_p,
inout [ 3:0] hps_ddr_dqs_n,
inout [ 31:0] hps_ddr_dq,
inout [ 3:0] hps_ddr_dbi_n,
input hps_ddr_rzq,
// hps-ethernet
input [ 0:0] hps_eth_rxclk,
input [ 0:0] hps_eth_rxctl,
input [ 3:0] hps_eth_rxd,
output [ 0:0] hps_eth_txclk,
output [ 0:0] hps_eth_txctl,
output [ 3:0] hps_eth_txd,
output [ 0:0] hps_eth_mdc,
inout [ 0:0] hps_eth_mdio,
// hps-sdio
output [ 0:0] hps_sdio_clk,
inout [ 0:0] hps_sdio_cmd,
inout [ 7:0] hps_sdio_d,
// hps-usb
input [ 0:0] hps_usb_clk,
input [ 0:0] hps_usb_dir,
input [ 0:0] hps_usb_nxt,
output [ 0:0] hps_usb_stp,
inout [ 7:0] hps_usb_d,
// hps-uart
input [ 0:0] hps_uart_rx,
output [ 0:0] hps_uart_tx,
// hps-i2c (shared w fmc-a, fmc-b)
inout [ 0:0] hps_i2c_sda,
inout [ 0:0] hps_i2c_scl,
// hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio,
// gpio (max-v-u21)
input [ 7:0] gpio_bd_i,
output [ 3:0] gpio_bd_o,
// ad9361-interface
input rx_clk_in,
input rx_frame_in,
input [ 5:0] rx_data_in,
output tx_clk_out,
output tx_frame_out,
output [ 5:0] tx_data_out,
output enable,
output txnrx,
output gpio_resetb,
output gpio_sync,
output gpio_en_agc,
output [ 3:0] gpio_ctl,
input [ 7:0] gpio_status,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [ 31:0] gpio_i;
wire [ 31:0] gpio_o;
// gpio (ad9361)
assign gpio_i[31:24] = gpio_o[31:24];
assign gpio_i[23:16] = gpio_status;
assign gpio_resetb = gpio_o[22];
assign gpio_sync = gpio_o[21];
assign gpio_en_agc = gpio_o[20];
assign gpio_ctl = gpio_o[19:16];
// gpio (max-v-u21)
assign gpio_i[15:8] = gpio_o[15:8];
assign gpio_i[ 7:0] = gpio_bd_i;
assign gpio_bd_o = gpio_o[3:0];
// instantiations
system_bd i_system_bd (
.ad9361_if_rx_clk_in_p (rx_clk_in),
.ad9361_if_rx_clk_in_n (1'b0),
.ad9361_if_rx_frame_in_p (rx_frame_in),
.ad9361_if_rx_frame_in_n (1'b0),
.ad9361_if_rx_data_in_p (rx_data_in),
.ad9361_if_rx_data_in_n (6'd0),
.ad9361_if_tx_clk_out_p (tx_clk_out),
.ad9361_if_tx_clk_out_n (),
.ad9361_if_tx_frame_out_p (tx_frame_out),
.ad9361_if_tx_frame_out_n (),
.ad9361_if_tx_data_out_p (tx_data_out),
.ad9361_if_tx_data_out_n (),
.ad9361_if_enable (enable),
.ad9361_if_txnrx (txnrx),
.delay_clk_clk (1'b0),
.hps_ddr_mem_ck (hps_ddr_clk_p),
.hps_ddr_mem_ck_n (hps_ddr_clk_n),
.hps_ddr_mem_a (hsp_ddr_a),
.hps_ddr_mem_act_n (hps_ddr_act_n),
.hps_ddr_mem_ba (hps_ddr_ba),
.hps_ddr_mem_bg (hps_ddr_bg),
.hps_ddr_mem_cke (hps_ddr_cke),
.hps_ddr_mem_cs_n (hps_ddr_cs_n),
.hps_ddr_mem_odt (hps_ddr_odt),
.hps_ddr_mem_reset_n (hps_ddr_reset_n),
.hps_ddr_mem_par (hps_ddr_par),
.hps_ddr_mem_alert_n (hps_ddr_alert_n),
.hps_ddr_mem_dqs (hps_ddr_dqs_p),
.hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
.hps_ddr_mem_dq (hps_ddr_dq),
.hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
.hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
.hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
.hps_gpio_gp_in (gpio_i),
.hps_gpio_gp_out (gpio_o),
.hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
.hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
.hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
.hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
.hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
.hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
.hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
.hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
.hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
.hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
.hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
.hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
.hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
.hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
.hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
.hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
.hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
.hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
.hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
.hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
.hps_spi0_mosi_o (spi_mosi),
.hps_spi0_miso_i (spi_miso),
.hps_spi0_ss_in_n (1'b1),
.hps_spi0_mosi_oe (),
.hps_spi0_ss0_n_o (spi_csn),
.hps_spi0_ss1_n_o (),
.hps_spi0_ss2_n_o (),
.hps_spi0_ss3_n_o (),
.hps_spi0_sclk_clk (spi_clk),
.hps_spi1_mosi_o (),
.hps_spi1_miso_i (1'b0),
.hps_spi1_ss_in_n (1'b1),
.hps_spi1_mosi_oe (),
.hps_spi1_ss0_n_o (),
.hps_spi1_ss1_n_o (),
.hps_spi1_ss2_n_o (),
.hps_spi1_ss3_n_o (),
.hps_spi1_sclk_clk (),
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.up_enable_up_enable (gpio_o[23]),
.up_txnrx_up_txnrx (gpio_o[24]));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ad9371
create_bd_port -dir I rx_ref_clk
create_bd_port -dir I rx_sysref
create_bd_port -dir I -from 1 -to 0 rx_p
create_bd_port -dir I -from 1 -to 0 rx_n
create_bd_port -dir O rx_sync
create_bd_port -dir I -from 1 -to 0 rx_os_p
create_bd_port -dir I -from 1 -to 0 rx_os_n
create_bd_port -dir O rx_os_sync
create_bd_port -dir I tx_ref_clk
create_bd_port -dir I tx_sysref
create_bd_port -dir O -from 3 -to 0 tx_p
create_bd_port -dir O -from 3 -to 0 tx_n
create_bd_port -dir I tx_sync
create_bd_port -dir I dac_fifo_bypass
# dma clock
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
ad_connect sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
# dac peripherals
set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
p_sys_dacfifo [current_bd_instance .] axi_ad9371_tx_fifo 128 17
set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_tx_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
# adc peripherals
set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd
set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_ad9371_rx_os_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_dma
set axi_ad9371_rx_os_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_os_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_os_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_os_dma
set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
# ad9371 gt & core
set axi_ad9371_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9371:1.0 axi_ad9371_core]
set axi_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9371_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9371_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_DATA_SEL_0 {3}] $axi_ad9371_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9371_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_DATA_SEL_1 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9371_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9371_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {5}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_ad9371_gt
set util_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_ad9371_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_gt
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_ad9371_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_gt
set_property -dict [list CONFIG.TX_ENABLE {1}] $util_ad9371_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_gt
set util_ad9371_os_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_os_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9371_os_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_os_gt
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad9371_os_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_os_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_os_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9371_os_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $util_ad9371_os_gt
# ad9371 data path clocks
set axi_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_tx_clkgen]
set_property -dict [list CONFIG.ID {2}] $axi_tx_clkgen
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_tx_clkgen
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_tx_clkgen
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_tx_clkgen
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_tx_clkgen
set axi_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_clkgen]
set_property -dict [list CONFIG.ID {2}] $axi_rx_clkgen
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_clkgen
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_clkgen
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_clkgen
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_clkgen
set axi_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_os_clkgen]
set_property -dict [list CONFIG.ID {2}] $axi_rx_os_clkgen
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_os_clkgen
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_os_clkgen
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_os_clkgen
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_os_clkgen
# connections (gt)
ad_connect util_ad9371_gt/qpll_ref_clk rx_ref_clk
ad_connect util_ad9371_gt/cpll_ref_clk tx_ref_clk
ad_connect util_ad9371_os_gt/qpll_ref_clk rx_ref_clk
ad_connect util_ad9371_os_gt/cpll_ref_clk tx_ref_clk
ad_connect axi_ad9371_gt/gt_qpll_0 util_ad9371_gt/gt_qpll_0
ad_connect axi_ad9371_gt/gt_pll_0 util_ad9371_gt/gt_pll_0
ad_connect axi_ad9371_gt/gt_pll_1 util_ad9371_gt/gt_pll_1
ad_connect axi_ad9371_gt/gt_pll_2 util_ad9371_gt/gt_pll_2
ad_connect axi_ad9371_gt/gt_pll_3 util_ad9371_gt/gt_pll_3
ad_connect axi_ad9371_gt/gt_rx_0 util_ad9371_gt/gt_rx_0
ad_connect axi_ad9371_gt/gt_rx_1 util_ad9371_gt/gt_rx_1
ad_connect axi_ad9371_gt/gt_rx_ip_0 axi_ad9371_rx_jesd/gt0_rx
ad_connect axi_ad9371_gt/gt_rx_ip_1 axi_ad9371_rx_jesd/gt1_rx
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_0 axi_ad9371_rx_jesd/rxencommaalign_out
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_1 axi_ad9371_rx_jesd/rxencommaalign_out
ad_connect axi_ad9371_gt/gt_rx_2 util_ad9371_os_gt/gt_rx_0
ad_connect axi_ad9371_gt/gt_rx_3 util_ad9371_os_gt/gt_rx_1
ad_connect axi_ad9371_gt/gt_rx_ip_2 axi_ad9371_rx_os_jesd/gt0_rx
ad_connect axi_ad9371_gt/gt_rx_ip_3 axi_ad9371_rx_os_jesd/gt1_rx
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_2 axi_ad9371_rx_os_jesd/rxencommaalign_out
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_3 axi_ad9371_rx_os_jesd/rxencommaalign_out
ad_connect axi_ad9371_gt/gt_tx_0 util_ad9371_gt/gt_tx_0
ad_connect axi_ad9371_gt/gt_tx_1 util_ad9371_gt/gt_tx_1
ad_connect axi_ad9371_gt/gt_tx_2 util_ad9371_gt/gt_tx_2
ad_connect axi_ad9371_gt/gt_tx_3 util_ad9371_gt/gt_tx_3
ad_connect axi_ad9371_gt/gt_tx_ip_0 axi_ad9371_tx_jesd/gt0_tx
ad_connect axi_ad9371_gt/gt_tx_ip_1 axi_ad9371_tx_jesd/gt1_tx
ad_connect axi_ad9371_gt/gt_tx_ip_2 axi_ad9371_tx_jesd/gt2_tx
ad_connect axi_ad9371_gt/gt_tx_ip_3 axi_ad9371_tx_jesd/gt3_tx
# connections (dac)
ad_connect util_ad9371_gt/tx_sysref tx_sysref
ad_connect util_ad9371_gt/tx_p tx_p
ad_connect util_ad9371_gt/tx_n tx_n
ad_connect util_ad9371_gt/tx_sync tx_sync
ad_connect util_ad9371_gt/tx_out_clk axi_tx_clkgen/clk
ad_connect axi_tx_clkgen/clk_0 util_ad9371_gt/tx_clk
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
ad_connect util_ad9371_gt/tx_ip_rst axi_ad9371_tx_jesd/tx_reset
ad_connect util_ad9371_gt/tx_ip_rst_done axi_ad9371_tx_jesd/tx_reset_done
ad_connect util_ad9371_gt/tx_ip_sysref axi_ad9371_tx_jesd/tx_sysref
ad_connect util_ad9371_gt/tx_ip_sync axi_ad9371_tx_jesd/tx_sync
ad_connect util_ad9371_gt/tx_ip_data axi_ad9371_tx_jesd/tx_tdata
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
ad_connect util_ad9371_gt/tx_data axi_ad9371_core/dac_tx_data
ad_connect axi_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
ad_connect axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0
ad_connect axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0
ad_connect axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0
ad_connect axi_ad9371_core/dac_valid_q0 util_ad9371_tx_upack/dac_valid_1
ad_connect axi_ad9371_core/dac_enable_q0 util_ad9371_tx_upack/dac_enable_1
ad_connect axi_ad9371_core/dac_data_q0 util_ad9371_tx_upack/dac_data_1
ad_connect axi_ad9371_core/dac_valid_i1 util_ad9371_tx_upack/dac_valid_2
ad_connect axi_ad9371_core/dac_enable_i1 util_ad9371_tx_upack/dac_enable_2
ad_connect axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_tx_fifo/dac_xfer_out
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dac_clk
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_tx_fifo/dac_valid
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_tx_fifo/dac_data
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dma_clk
ad_connect util_ad9371_gt/tx_rst axi_ad9371_tx_fifo/dma_rst
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
ad_connect axi_ad9371_tx_fifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
ad_connect axi_ad9371_tx_fifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
ad_connect axi_ad9371_tx_fifo/dma_data axi_ad9371_tx_dma/m_axis_data
ad_connect axi_ad9371_tx_fifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
ad_connect axi_ad9371_tx_fifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
# connections (adc)
ad_connect util_ad9371_gt/rx_sysref rx_sysref
ad_connect util_ad9371_gt/rx_p rx_p
ad_connect util_ad9371_gt/rx_n rx_n
ad_connect util_ad9371_gt/rx_sync rx_sync
ad_connect util_ad9371_os_gt/rx_p rx_os_p
ad_connect util_ad9371_os_gt/rx_n rx_os_n
ad_connect util_ad9371_os_gt/rx_sysref rx_sysref
ad_connect util_ad9371_os_gt/rx_sync rx_os_sync
ad_connect util_ad9371_gt/rx_out_clk axi_rx_clkgen/clk
ad_connect axi_rx_clkgen/clk_0 util_ad9371_gt/rx_clk
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
ad_connect util_ad9371_gt/rx_ip_rst axi_ad9371_rx_jesd/rx_reset
ad_connect util_ad9371_gt/rx_ip_rst_done axi_ad9371_rx_jesd/rx_reset_done
ad_connect util_ad9371_gt/rx_ip_sysref axi_ad9371_rx_jesd/rx_sysref
ad_connect util_ad9371_gt/rx_ip_sync axi_ad9371_rx_jesd/rx_sync
ad_connect util_ad9371_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
ad_connect util_ad9371_gt/rx_ip_data axi_ad9371_rx_jesd/rx_tdata
ad_connect util_ad9371_os_gt/rx_out_clk axi_rx_os_clkgen/clk
ad_connect axi_rx_os_clkgen/clk_0 util_ad9371_os_gt/rx_clk
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
ad_connect util_ad9371_os_gt/rx_ip_rst axi_ad9371_rx_os_jesd/rx_reset
ad_connect util_ad9371_os_gt/rx_ip_rst_done axi_ad9371_rx_os_jesd/rx_reset_done
ad_connect util_ad9371_os_gt/rx_ip_sysref axi_ad9371_rx_os_jesd/rx_sysref
ad_connect util_ad9371_os_gt/rx_ip_sync axi_ad9371_rx_os_jesd/rx_sync
ad_connect util_ad9371_os_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
ad_connect util_ad9371_os_gt/rx_ip_data axi_ad9371_rx_os_jesd/rx_tdata
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
ad_connect util_ad9371_gt/rx_data axi_ad9371_core/adc_rx_data
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
ad_connect util_ad9371_os_gt/rx_data axi_ad9371_core/adc_rx_os_data
ad_connect axi_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
ad_connect util_ad9371_gt/rx_rst util_ad9371_rx_cpack/adc_rst
ad_connect axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0
ad_connect axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0
ad_connect axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0
ad_connect axi_ad9371_core/adc_enable_q0 util_ad9371_rx_cpack/adc_enable_1
ad_connect axi_ad9371_core/adc_valid_q0 util_ad9371_rx_cpack/adc_valid_1
ad_connect axi_ad9371_core/adc_data_q0 util_ad9371_rx_cpack/adc_data_1
ad_connect axi_ad9371_core/adc_enable_i1 util_ad9371_rx_cpack/adc_enable_2
ad_connect axi_ad9371_core/adc_valid_i1 util_ad9371_rx_cpack/adc_valid_2
ad_connect axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2
ad_connect axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3
ad_connect axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3
ad_connect axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
ad_connect util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en
ad_connect util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync
ad_connect util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din
ad_connect axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf
ad_connect axi_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
ad_connect util_ad9371_os_gt/rx_rst util_ad9371_rx_os_cpack/adc_rst
ad_connect axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0
ad_connect axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0
ad_connect axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0
ad_connect axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1
ad_connect axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1
ad_connect axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
ad_connect util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
ad_connect util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
ad_connect util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
ad_connect axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
ad_connect axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_ad9371_gt
ad_cpu_interconnect 0x44A00000 axi_ad9371_core
ad_cpu_interconnect 0x43C00000 axi_tx_clkgen
ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
ad_cpu_interconnect 0x43C10000 axi_rx_clkgen
ad_cpu_interconnect 0x43C20000 axi_rx_os_clkgen
ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd
ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
# gt uses hp0, and 100MHz clock for both DRP and AXI4
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
# interconnect (mem/dac)
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_dma_clk axi_ad9371_tx_dma/m_src_axi
ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/ARESETN
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/M00_ARESETN
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/S00_ARESETN
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/ARESETN
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/M00_ARESETN
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S00_ARESETN
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S01_ARESETN
ad_connect sys_dma_resetn axi_hp1_interconnect/ARESETN
ad_connect sys_dma_resetn axi_hp1_interconnect/M00_ARESETN
ad_connect sys_dma_resetn axi_hp1_interconnect/S00_ARESETN
ad_connect sys_dma_resetn axi_hp2_interconnect/ARESETN
ad_connect sys_dma_resetn axi_hp2_interconnect/M00_ARESETN
ad_connect sys_dma_resetn axi_hp2_interconnect/S00_ARESETN
ad_connect sys_dma_resetn axi_hp2_interconnect/S01_ARESETN
# interrupts
ad_cpu_interrupt ps-11 mb-11 axi_ad9371_rx_os_dma/irq
ad_cpu_interrupt ps-12 mb-12 axi_ad9371_tx_dma/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad9371_rx_dma/irq
# ila
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
ad_connect axi_rx_clkgen/clk_0 ila_adc/clk
ad_connect axi_ad9371_core/adc_data_i0 ila_adc/probe0
ad_connect axi_ad9371_core/adc_data_q0 ila_adc/probe1
ad_connect axi_ad9371_core/adc_data_i1 ila_adc/probe2
ad_connect axi_ad9371_core/adc_data_q1 ila_adc/probe3
set bsplit_os_adc_0 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_0]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_0
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_0
set bsplit_os_adc_1 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_1]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_1
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $bsplit_os_adc_1
set ila_os_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_os_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_os_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {6}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_os_adc
set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_os_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_os_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_os_adc
ad_connect axi_ad9371_core/adc_os_data_i0 bsplit_os_adc_0/data
ad_connect axi_ad9371_core/adc_os_data_q0 bsplit_os_adc_1/data
ad_connect axi_rx_os_clkgen/clk_0 ila_os_adc/clk
ad_connect axi_ad9371_core/adc_os_valid_i0 ila_os_adc/probe0
ad_connect bsplit_os_adc_0/split_data_0 ila_os_adc/probe1
ad_connect bsplit_os_adc_0/split_data_1 ila_os_adc/probe2
ad_connect axi_ad9371_core/adc_os_valid_q0 ila_os_adc/probe3
ad_connect bsplit_os_adc_1/split_data_0 ila_os_adc/probe4
ad_connect bsplit_os_adc_1/split_data_1 ila_os_adc/probe5

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
source ../common/adrv9371x_bd.tcl

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# ad9371
set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
set_property -dict {PACKAGE_PIN AA8 } [get_ports ref_clk1_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports ref_clk1_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer)
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G36 FMC_HPC_LA33_P
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G37 FMC_HPC_LA33_N
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports ad9371_tx1_enable] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports ad9371_tx2_enable] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports ad9371_rx1_enable] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports ad9371_rx2_enable] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9371_test] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17] ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16] ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18] ; ## D12 FMC_HPC_LA05_N
# clocks
create_clock -name tx_ref_clk -period 6.25 [get_ports ref_clk0_p]
create_clock -name rx_ref_clk -period 6.25 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
# sync is also sampled at the cpu clock by the ip.
set_false_path -from [get_cells -hier -filter {name =~ *axi_ad9371_gt*tx_ip_sync* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *axi_ad9371_tx_jesd*sync_tx_sync*data_sync* && IS_SEQUENTIAL}]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create adrv9371x_zc706
adi_project_files adrv9371x_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run adrv9371x_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
ref_clk0_p,
ref_clk0_n,
ref_clk1_p,
ref_clk1_n,
rx_data_p,
rx_data_n,
tx_data_p,
tx_data_n,
rx_sync_p,
rx_sync_n,
rx_os_sync_p,
rx_os_sync_n,
tx_sync_p,
tx_sync_n,
sysref_p,
sysref_n,
spi_csn_ad9528,
spi_csn_ad9371,
spi_clk,
spi_mosi,
spi_miso,
ad9528_reset_b,
ad9528_sysref_req,
ad9371_tx1_enable,
ad9371_tx2_enable,
ad9371_rx1_enable,
ad9371_rx2_enable,
ad9371_test,
ad9371_reset_b,
ad9371_gpint,
ad9371_gpio_00,
ad9371_gpio_01,
ad9371_gpio_02,
ad9371_gpio_03,
ad9371_gpio_04,
ad9371_gpio_05,
ad9371_gpio_06,
ad9371_gpio_07,
ad9371_gpio_15,
ad9371_gpio_08,
ad9371_gpio_09,
ad9371_gpio_10,
ad9371_gpio_11,
ad9371_gpio_12,
ad9371_gpio_14,
ad9371_gpio_13,
ad9371_gpio_17,
ad9371_gpio_16,
ad9371_gpio_18);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input ref_clk0_p;
input ref_clk0_n;
input ref_clk1_p;
input ref_clk1_n;
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
output [ 3:0] tx_data_p;
output [ 3:0] tx_data_n;
output rx_sync_p;
output rx_sync_n;
output rx_os_sync_p;
output rx_os_sync_n;
input tx_sync_p;
input tx_sync_n;
input sysref_p;
input sysref_n;
output spi_csn_ad9528;
output spi_csn_ad9371;
output spi_clk;
output spi_mosi;
input spi_miso;
inout ad9528_reset_b;
inout ad9528_sysref_req;
inout ad9371_tx1_enable;
inout ad9371_tx2_enable;
inout ad9371_rx1_enable;
inout ad9371_rx2_enable;
inout ad9371_test;
inout ad9371_reset_b;
inout ad9371_gpint;
inout ad9371_gpio_00;
inout ad9371_gpio_01;
inout ad9371_gpio_02;
inout ad9371_gpio_03;
inout ad9371_gpio_04;
inout ad9371_gpio_05;
inout ad9371_gpio_06;
inout ad9371_gpio_07;
inout ad9371_gpio_15;
inout ad9371_gpio_08;
inout ad9371_gpio_09;
inout ad9371_gpio_10;
inout ad9371_gpio_11;
inout ad9371_gpio_12;
inout ad9371_gpio_14;
inout ad9371_gpio_13;
inout ad9371_gpio_17;
inout ad9371_gpio_16;
inout ad9371_gpio_18;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire sysref;
wire ad9371_dac_fifo_bypass_s;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE2 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
.dio_t ({gpio_t[60:32]}),
.dio_i ({gpio_o[60:32]}),
.dio_o ({gpio_i[60:32]}),
.dio_p ({ ad9371_dac_fifo_bypass_s, // 60
ad9528_reset_b, // 59
ad9528_sysref_req, // 58
ad9371_tx1_enable, // 57
ad9371_tx2_enable, // 56
ad9371_rx1_enable, // 55
ad9371_rx2_enable, // 54
ad9371_test, // 53
ad9371_reset_b, // 52
ad9371_gpint, // 51
ad9371_gpio_00, // 50
ad9371_gpio_01, // 49
ad9371_gpio_02, // 48
ad9371_gpio_03, // 47
ad9371_gpio_04, // 46
ad9371_gpio_05, // 45
ad9371_gpio_06, // 44
ad9371_gpio_07, // 43
ad9371_gpio_15, // 42
ad9371_gpio_08, // 41
ad9371_gpio_09, // 40
ad9371_gpio_10, // 39
ad9371_gpio_11, // 38
ad9371_gpio_12, // 37
ad9371_gpio_14, // 36
ad9371_gpio_13, // 35
ad9371_gpio_17, // 34
ad9371_gpio_16, // 33
ad9371_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.rx_n (rx_data_n[1:0]),
.rx_os_n (rx_data_n[3:2]),
.rx_os_p (rx_data_p[3:2]),
.rx_os_sync (rx_os_sync),
.rx_p (rx_data_p[1:0]),
.rx_ref_clk (ref_clk1),
.rx_sync (rx_sync),
.rx_sysref (sysref),
.spdif (spdif),
.spi0_clk_i (spi_clk),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn_ad9528),
.spi0_csn_1_o (spi_csn_ad9371),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (spi_mosi),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'd0),
.spi1_clk_o (1'd0),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'd0),
.spi1_sdo_i (1'd0),
.spi1_sdo_o (),
.tx_n (tx_data_n),
.tx_p (tx_data_p),
.tx_ref_clk (ref_clk1),
.tx_sync (tx_sync),
.tx_sysref (sysref),
.dac_fifo_bypass(ad9371_dac_fifo_bypass_s));
endmodule
// ***************************************************************************
// ***************************************************************************