From f86ae28e505930a2211cabed678e31ecbd6c1134 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 28 Sep 2020 19:24:46 +0100 Subject: [PATCH] spi_engine/data_reorder: Initial commit In case of multiple SDI (MISO) lanes, the samples arrives in a parallel fashion. For example in case of 4 MISO line, at the first latching clock edge 4 bits of a sample will be saved, one bit into each shift register. The data reorder module reconstruct the incoming samples from the AXI stream of the offload module. --- library/Makefile | 2 + library/spi_engine/spi_axis_reorder/Makefile | 13 ++ .../spi_axis_reorder/spi_axis_reorder.v | 140 ++++++++++++++++++ .../spi_axis_reorder/spi_axis_reorder_ip.tcl | 33 +++++ 4 files changed, 188 insertions(+) create mode 100644 library/spi_engine/spi_axis_reorder/Makefile create mode 100644 library/spi_engine/spi_axis_reorder/spi_axis_reorder.v create mode 100644 library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl diff --git a/library/Makefile b/library/Makefile index f164964f7..ad0a976ee 100644 --- a/library/Makefile +++ b/library/Makefile @@ -90,6 +90,7 @@ clean: $(MAKE) -C jesd204/jesd204_versal_gt_adapter_rx clean $(MAKE) -C jesd204/jesd204_versal_gt_adapter_tx clean $(MAKE) -C spi_engine/axi_spi_engine clean + $(MAKE) -C spi_engine/spi_axis_reorder clean $(MAKE) -C spi_engine/spi_engine_execution clean $(MAKE) -C spi_engine/spi_engine_interconnect clean $(MAKE) -C spi_engine/spi_engine_offload clean @@ -211,6 +212,7 @@ lib: $(MAKE) -C jesd204/jesd204_versal_gt_adapter_rx $(MAKE) -C jesd204/jesd204_versal_gt_adapter_tx $(MAKE) -C spi_engine/axi_spi_engine + $(MAKE) -C spi_engine/spi_axis_reorder $(MAKE) -C spi_engine/spi_engine_execution $(MAKE) -C spi_engine/spi_engine_interconnect $(MAKE) -C spi_engine/spi_engine_offload diff --git a/library/spi_engine/spi_axis_reorder/Makefile b/library/spi_engine/spi_axis_reorder/Makefile new file mode 100644 index 000000000..d4c49fdbc --- /dev/null +++ b/library/spi_engine/spi_axis_reorder/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := spi_axis_reorder + +GENERIC_DEPS += spi_axis_reorder.v + +XILINX_DEPS += spi_axis_reorder_ip.tcl + +include ../../scripts/library.mk diff --git a/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v new file mode 100644 index 000000000..33a3b2f36 --- /dev/null +++ b/library/spi_engine/spi_axis_reorder/spi_axis_reorder.v @@ -0,0 +1,140 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Re-ordering module for Flexi-SPI +// +module spi_axis_reorder #( + + parameter [3:0] NUM_OF_LANES = 2) ( + + input axis_aclk, + input axis_aresetn, + + input s_axis_valid, + output s_axis_ready, + input [(NUM_OF_LANES * 32)-1:0] s_axis_data, + + output m_axis_valid, + input m_axis_ready, + output [63:0] m_axis_data +); + + // re-packager is always ready + assign s_axis_ready = 1'b1; + + genvar i, j; + generate + if (NUM_OF_LANES == 1) begin : g_reorder_1_lane_interleaved + + reg wr_addr = 0; + reg [63:0] axis_data_int; + reg mem_is_full; + + // address control + // NOTE: ready is ignored, taking the fact that the module is always ready + always @(posedge axis_aclk) begin + if (axis_aresetn == 1'b0) begin + wr_addr <= 1'b0; + axis_data_int <= 64'b0; + end else begin + if ((s_axis_valid == 1'b1) && (s_axis_ready == 1'b1)) begin + wr_addr <= wr_addr + 1'b1; + axis_data_int <= (wr_addr) ? {s_axis_data, axis_data_int[31:0]} : + {axis_data_int[63:32], s_axis_data}; + end + end + end + + // latch the state of the memory + always @(posedge axis_aclk) begin + if (axis_aresetn == 1'b0) begin + mem_is_full <= 1'b0; + end else begin + if ((wr_addr == 1'b1) && (s_axis_valid == 1'b1)) begin + mem_is_full <= 1'b1; + end else begin + mem_is_full <= 1'b0; + end + end + end + + // reorder the interleaved data + assign m_axis_valid = mem_is_full; + for (i=0; i<32; i=i+1) begin + assign m_axis_data[ i] = axis_data_int[2*i+1]; + assign m_axis_data[32+i] = axis_data_int[2*i]; + end + + end else if (NUM_OF_LANES == 2) begin : g_reorder_2_lanes + + assign m_axis_valid = s_axis_valid; + assign m_axis_data = s_axis_data; + + end else if (NUM_OF_LANES == 4) begin : g_reorder_4_lanes + + assign m_axis_valid = s_axis_valid; + for (i=0; i<16; i=i+1) begin + // first channel + assign m_axis_data[2*i ] = s_axis_data[32+i]; + assign m_axis_data[2*i+1] = s_axis_data[ i]; + // second channel + assign m_axis_data[2*i+32] = s_axis_data[96+i]; + assign m_axis_data[2*i+33] = s_axis_data[64+i]; + end + + end else if (NUM_OF_LANES == 8) begin : g_reorder_8_lanes + + assign m_axis_valid = s_axis_valid; + for (i=0; i<8; i=i+1) begin + // first channel + assign m_axis_data[4*i ] = s_axis_data[96+i]; + assign m_axis_data[4*i+1] = s_axis_data[64+i]; + assign m_axis_data[4*i+2] = s_axis_data[32+i]; + assign m_axis_data[4*i+3] = s_axis_data[ i]; + // second channel + assign m_axis_data[4*i+32] = s_axis_data[224+i]; + assign m_axis_data[4*i+33] = s_axis_data[192+i]; + assign m_axis_data[4*i+34] = s_axis_data[160+i]; + assign m_axis_data[4*i+35] = s_axis_data[128+i]; + end + + end else begin + // WARNING: Invalid configuration, leave everybody in the air + end + endgenerate + +endmodule diff --git a/library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl b/library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl new file mode 100644 index 000000000..599396ab4 --- /dev/null +++ b/library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl @@ -0,0 +1,33 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create spi_axis_reorder +adi_ip_files spi_axis_reorder [list \ + "spi_axis_reorder.v" \ +] + +adi_ip_properties_lite spi_axis_reorder +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +# Interface definitions + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"}] + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"}] + +adi_add_bus_clock "axis_aclk" "s_axis:m_axis" "axis_aresetn" + +ipx::save_core [ipx::current_core] +