daq2/kcu105: interrupt updates
Rejeesh Kutty
parent
4788d09620
commit
f83622a2e6
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@ -28,21 +28,6 @@ set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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# interrupts
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set timer_irq [create_bd_port -dir O timer_irq]
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set eth_irq [create_bd_port -dir O eth_irq]
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set eth_dma_mm2s_irq [create_bd_port -dir O eth_dma_mm2s_irq]
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set eth_dma_s2mm_irq [create_bd_port -dir O eth_dma_s2mm_irq]
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set uart_irq [create_bd_port -dir O uart_irq]
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set gpio_lcd_irq [create_bd_port -dir O gpio_lcd_irq]
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set gpio_sw_irq [create_bd_port -dir O gpio_sw_irq]
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set spdif_dma_irq [create_bd_port -dir O spdif_dma_irq]
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set iic_irq [create_bd_port -dir O iic_irq]
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set hdmi_dma_irq [create_bd_port -dir O hdmi_dma_irq]
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set mb_axi_intr [create_bd_port -dir I -from 31 -to 0 -type intr mb_axi_intr]
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# spdif audio
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set spdif [create_bd_port -dir O spdif]
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@ -192,6 +177,9 @@ set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
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set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
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set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {32}] $sys_concat_intc
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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@ -244,8 +232,7 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd
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connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
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connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
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connect_bd_net -net sys_concat_intr [get_bd_ports mb_axi_intr] [get_bd_pins axi_intc/intr]
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set_property -dict [list CONFIG.PortWidth {32}] [get_bd_ports mb_axi_intr]
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connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr]
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# defaults (peripherals)
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@ -373,16 +360,21 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sy
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# defaults (interrupts)
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connect_bd_net -net sys_base_intr_00 [get_bd_ports timer_irq] [get_bd_pins axi_timer/interrupt]
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connect_bd_net -net sys_base_intr_01 [get_bd_ports eth_irq] [get_bd_pins axi_ethernet/interrupt]
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connect_bd_net -net sys_base_intr_02 [get_bd_ports eth_dma_mm2s_irq] [get_bd_pins axi_ethernet_dma/mm2s_introut]
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connect_bd_net -net sys_base_intr_03 [get_bd_ports eth_dma_s2mm_irq] [get_bd_pins axi_ethernet_dma/s2mm_introut]
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connect_bd_net -net sys_base_intr_04 [get_bd_ports uart_irq] [get_bd_pins axi_uart/interrupt]
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connect_bd_net -net sys_base_intr_05 [get_bd_ports gpio_lcd_irq] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
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connect_bd_net -net sys_base_intr_06 [get_bd_ports gpio_sw_irq] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
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connect_bd_net -net sys_base_intr_07 [get_bd_ports spdif_dma_irq] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
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connect_bd_net -net sys_base_intr_08 [get_bd_ports iic_irq] [get_bd_pins axi_hdmi_dma/mm2s_introut]
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connect_bd_net -net sys_base_intr_09 [get_bd_ports hdmi_dma_irq] [get_bd_pins axi_iic_main/iic2intc_irpt]
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connect_bd_net [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt]
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connect_bd_net [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt]
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connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut]
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connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut]
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connect_bd_net [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_uart/interrupt]
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connect_bd_net [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
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connect_bd_net [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
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connect_bd_net [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
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connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s_introut]
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connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt]
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for {set intc_index 10} {$intc_index < 32} {incr intc_index} {
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set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}]
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connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}]
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}
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# defaults (ddr)
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@ -75,6 +75,11 @@ if {$sys_zynq == 1} {
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set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
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}
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set axi_ad9144_dma_intr [create_bd_port -dir O axi_ad9144_dma_intr]
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set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr]
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set axi_daq2_spi_intr [create_bd_port -dir O axi_daq2_spi_intr ]
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set axi_daq2_gpio_intr [create_bd_port -dir O axi_daq2_gpio_intr ]
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# dac peripherals
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set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
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@ -185,7 +190,6 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
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set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
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}
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if {$sys_zynq == 1} {
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@ -248,12 +252,6 @@ if {$sys_zynq == 0} {
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t]
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}
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if {$sys_zynq == 0} {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2]
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delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3]
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}
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# connections (gt)
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connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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@ -299,7 +297,7 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en]
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connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout]
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connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow]
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connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In12]
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connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_ports axi_ad9144_dma_intr]
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# connections (adc)
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@ -339,7 +337,7 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
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connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
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connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
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connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
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connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr]
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# dac/adc clocks
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@ -403,8 +401,8 @@ if {$sys_zynq == 0} {
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn]
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connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
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connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
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connect_bd_net -net axi_daq2_spi_intr [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_ports axi_daq2_spi_intr]
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connect_bd_net -net axi_daq2_gpio_intr [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_ports axi_daq2_gpio_intr]
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}
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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@ -261,6 +261,7 @@ module system_top (
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wire [ 4:0] gpio_status_i;
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wire [ 4:0] gpio_status_o;
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wire [ 4:0] gpio_status_t;
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wire [31:0] mb_intrs;
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// adc-dac data
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@ -454,6 +455,10 @@ module system_top (
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.adc_enable_1 (adc_enable_1),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.axi_ad9144_dma_intr (mb_intrs[13]),
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.axi_ad9680_dma_intr (mb_intrs[12]),
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.axi_daq2_gpio_intr (mb_intrs[11]),
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.axi_daq2_spi_intr (mb_intrs[10]),
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.c0_ddr4_act_n (ddr4_act_n),
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.c0_ddr4_adr (ddr4_addr),
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.c0_ddr4_ba (ddr4_ba),
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@ -500,6 +505,28 @@ module system_top (
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.mb_intr_10 (mb_intrs[10]),
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.mb_intr_11 (mb_intrs[11]),
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.mb_intr_12 (mb_intrs[12]),
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.mb_intr_13 (mb_intrs[13]),
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.mb_intr_14 (mb_intrs[14]),
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.mb_intr_15 (mb_intrs[15]),
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.mb_intr_16 (mb_intrs[16]),
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.mb_intr_17 (mb_intrs[17]),
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.mb_intr_18 (mb_intrs[18]),
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.mb_intr_19 (mb_intrs[19]),
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.mb_intr_20 (mb_intrs[20]),
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.mb_intr_21 (mb_intrs[21]),
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.mb_intr_22 (mb_intrs[22]),
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.mb_intr_23 (mb_intrs[23]),
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.mb_intr_24 (mb_intrs[24]),
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.mb_intr_25 (mb_intrs[25]),
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.mb_intr_26 (mb_intrs[26]),
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.mb_intr_27 (mb_intrs[27]),
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.mb_intr_28 (mb_intrs[28]),
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.mb_intr_29 (mb_intrs[29]),
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.mb_intr_30 (mb_intrs[30]),
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.mb_intr_31 (mb_intrs[31]),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.phy_clk_clk_n (phy_clk_n),
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@ -532,8 +559,7 @@ module system_top (
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.tx_sync (tx_sync),
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.tx_sysref (tx_sysref),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.unc_int4 (1'b0));
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.uart_sout (uart_sout));
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endmodule
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