lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera

main
Istvan Csomortani 2016-08-05 17:19:30 +03:00
parent b806fa3b42
commit f784557895
4 changed files with 0 additions and 4 deletions

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@ -7,7 +7,6 @@ project_new arradio_c5soc -overwrite
source "../../common/c5soc/c5soc_system_assign.tcl"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top

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@ -6,7 +6,6 @@ project_new daq2_a10gx -overwrite
source "../../common/a10gx/a10gx_system_assign.tcl"
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys

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@ -9,7 +9,6 @@ set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v

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@ -9,7 +9,6 @@ set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5soc;../..
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5soc/;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v