signal tap removed
parent
19bf05c740
commit
f64df40a0a
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@ -2021,12 +2021,10 @@
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<module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
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<module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
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<parameter name="CH_CNT" value="2" />
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<parameter name="CH_CNT" value="2" />
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<parameter name="CH_DW" value="32" />
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<parameter name="CH_DW" value="32" />
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<parameter name="ST_DEPTH" value="1024" />
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</module>
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</module>
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<module name="util_cpack_1" kind="util_cpack" version="1.0" enabled="1">
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<module name="util_cpack_1" kind="util_cpack" version="1.0" enabled="1">
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<parameter name="CH_CNT" value="2" />
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<parameter name="CH_CNT" value="2" />
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<parameter name="CH_DW" value="32" />
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<parameter name="CH_DW" value="32" />
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<parameter name="ST_DEPTH" value="1024" />
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</module>
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</module>
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<module
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<module
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name="util_jesd_align_0"
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name="util_jesd_align_0"
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@ -8,7 +8,6 @@ source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
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set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
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set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
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set_global_assignment -name QSYS_FILE system_stap.qsys
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# reference clock
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# reference clock
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@ -59,7 +58,7 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity top_level
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set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr
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execute_flow -compile
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execute_flow -compile
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