diff --git a/projects/fmcjesdadc1/a5gt/system_bd.qsys b/projects/fmcjesdadc1/a5gt/system_bd.qsys
index a925b7f4e..afe224f4e 100644
--- a/projects/fmcjesdadc1/a5gt/system_bd.qsys
+++ b/projects/fmcjesdadc1/a5gt/system_bd.qsys
@@ -2021,12 +2021,10 @@
  <module name="util_cpack_0" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CH_CNT" value="2" />
   <parameter name="CH_DW" value="32" />
-  <parameter name="ST_DEPTH" value="1024" />
  </module>
  <module name="util_cpack_1" kind="util_cpack" version="1.0" enabled="1">
   <parameter name="CH_CNT" value="2" />
   <parameter name="CH_DW" value="32" />
-  <parameter name="ST_DEPTH" value="1024" />
  </module>
  <module
    name="util_jesd_align_0"
diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl
index e656a955f..f2ca2c2bb 100755
--- a/projects/fmcjesdadc1/a5gt/system_project.tcl
+++ b/projects/fmcjesdadc1/a5gt/system_project.tcl
@@ -8,7 +8,6 @@ source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
 
 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
 set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
-set_global_assignment -name QSYS_FILE system_stap.qsys
 
 # reference clock
 
@@ -59,7 +58,7 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
 
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_cntrl
 set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xfer_status
-set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity top_level
+set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to * -entity up_xcvr
 
 execute_flow -compile