From f647dd4c0ad8d3cc4829807f7709ee76838c7ea0 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 4 Apr 2018 16:27:49 +0200 Subject: [PATCH] xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen --- library/xilinx/util_adxcvr/util_adxcvr.v | 68 +++++++++++++++----- library/xilinx/util_adxcvr/util_adxcvr_xch.v | 16 +++-- 2 files changed, 60 insertions(+), 24 deletions(-) diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index eddea47ea..f803092b4 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -59,6 +59,7 @@ module util_adxcvr #( parameter integer TX_NUM_OF_LANES = 8, parameter integer TX_OUT_DIV = 1, parameter integer TX_CLK25_DIV = 20, + parameter integer TX_LANE_INVERT = 0, // rx-configuration @@ -67,7 +68,8 @@ module util_adxcvr #( parameter integer RX_CLK25_DIV = 20, parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, parameter [31:0] RX_PMA_CFG = 32'h001e7080, - parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020) ( + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, + parameter integer RX_LANE_INVERT = 0) ( input up_rstn, input up_clk, @@ -1045,11 +1047,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 0) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 0) & 1)) i_xch_0 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1138,11 +1142,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 1) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 1) & 1)) i_xch_1 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1231,11 +1237,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 2) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 2) & 1)) i_xch_2 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1324,11 +1332,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 3) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 3) & 1)) i_xch_3 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1447,11 +1457,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 4) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 4) & 1)) i_xch_4 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1540,11 +1552,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 5) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 5) & 1)) i_xch_5 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1633,11 +1647,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 6) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 6) & 1)) i_xch_6 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1726,11 +1742,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 7) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 7) & 1)) i_xch_7 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1849,11 +1867,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 8) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 8) & 1)) i_xch_8 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -1942,11 +1962,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 9) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 9) & 1)) i_xch_9 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2035,11 +2057,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 10) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 10) & 1)) i_xch_10 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2128,11 +2152,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 11) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 11) & 1)) i_xch_11 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2251,11 +2277,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 12) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 12) & 1)) i_xch_12 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2344,11 +2372,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 13) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 13) & 1)) i_xch_13 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2437,11 +2467,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 14) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 14) & 1)) i_xch_14 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2530,11 +2562,13 @@ module util_adxcvr #( .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 15) & 1), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), - .RX_CDR_CFG (RX_CDR_CFG)) + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 15) & 1)) i_xch_15 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index 222f49326..40cc9106b 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -46,12 +46,14 @@ module util_adxcvr_xch #( parameter integer TX_OUT_DIV = 1, parameter integer TX_CLK25_DIV = 20, + parameter integer TX_POLARITY = 0, parameter integer RX_OUT_DIV = 1, parameter integer RX_CLK25_DIV = 20, parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, parameter [31:0] RX_PMA_CFG = 32'h001e7080, - parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020) ( + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, + parameter integer RX_POLARITY = 0) ( // pll interface @@ -658,7 +660,7 @@ module util_adxcvr_xch #( .RXPHDLYRESET (1'h0), .RXPHOVRDEN (1'h0), .RXPMARESET (1'h0), - .RXPOLARITY (1'h0), + .RXPOLARITY (RX_POLARITY), .RXPRBSCNTRESET (1'h0), .RXPRBSERR (), .RXPRBSSEL (3'h0), @@ -715,7 +717,7 @@ module util_adxcvr_xch #( .TXPHOVRDEN (1'h0), .TXPISOPD (1'h0), .TXPMARESET (1'h0), - .TXPOLARITY (1'h0), + .TXPOLARITY (TX_POLARITY), .TXPOSTCURSOR (5'h0), .TXPOSTCURSORINV (1'h0), .TXPRBSFORCEERR (1'h0), @@ -1369,7 +1371,7 @@ module util_adxcvr_xch #( .RXPLLCLKSEL (rx_pll_clk_sel_s), .RXPMARESET (1'h0), .RXPMARESETDONE (), - .RXPOLARITY (1'h0), + .RXPOLARITY (RX_POLARITY), .RXPRBSCNTRESET (1'h0), .RXPRBSERR (), .RXPRBSLOCKED (), @@ -1460,7 +1462,7 @@ module util_adxcvr_xch #( .TXPLLCLKSEL (tx_pll_clk_sel_s), .TXPMARESET (1'h0), .TXPMARESETDONE (), - .TXPOLARITY (1'h0), + .TXPOLARITY (TX_POLARITY), .TXPOSTCURSOR (5'h0), .TXPOSTCURSORINV (1'h0), .TXPRBSFORCEERR (1'h0), @@ -2244,7 +2246,7 @@ module util_adxcvr_xch #( .RXPLLCLKSEL (rx_pll_clk_sel_s), .RXPMARESET (1'd0), .RXPMARESETDONE (), - .RXPOLARITY (1'd0), + .RXPOLARITY (RX_POLARITY), .RXPRBSCNTRESET (1'd0), .RXPRBSERR (), .RXPRBSLOCKED (), @@ -2343,7 +2345,7 @@ module util_adxcvr_xch #( .TXPLLCLKSEL (tx_pll_clk_sel_s), .TXPMARESET (1'd0), .TXPMARESETDONE (), - .TXPOLARITY (1'd0), + .TXPOLARITY (TX_POLARITY), .TXPOSTCURSOR (5'd0), .TXPRBSFORCEERR (1'd0), .TXPRBSSEL (4'd0),