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intel_mem_asym: Update the interface definitions 

The ram_2port IP has different interface names in Quartus PRO and
Quartus Standard.

Update the interface names for the support Quartus PRO.
main
Istvan Csomortani 2019-07-11 08:47:28 +01:00 committed by Adrian Costina
parent 2198320981
commit f624d5df40
4 changed files with 36 additions and 25 deletions
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14
library/intel/avl_dacfifo/avl_dacfifo_rd.v
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@ -159,13 +159,13 @@ module avl_dacfifo_rd #(
// interface
ad_mem_asym_rd i_mem_asym (
.mem_i_wrclock (avl_clk),
.mem_i_wren (avl_readdatavalid),
.mem_i_wraddress (avl_mem_waddr),
.mem_i_datain (avl_data),
.mem_i_rdclock (dac_clk),
.mem_i_rdaddress (dac_mem_raddr),
.mem_o_dataout (dac_mem_data_s));
.mem_i_wrclock_clk (avl_clk),
.mem_i_wren_wren (avl_readdatavalid),
.mem_i_wraddress_wraddress (avl_mem_waddr),
.mem_i_datain_datain (avl_data),
.mem_i_rdclock_clk (dac_clk),
.mem_i_rdaddress_rdaddress (dac_mem_raddr),
.mem_o_dataout_dataout (dac_mem_data_s));
// the fifo reset is the dma_xfer_req

14
library/intel/avl_dacfifo/avl_dacfifo_wr.v
View File

@ -148,13 +148,13 @@ module avl_dacfifo_wr #(
// interface
ad_mem_asym_wr i_mem_asym (
.mem_i_wrclock (dma_clk),
.mem_i_wren (dma_mem_wea_s),
.mem_i_wraddress (dma_mem_waddr),
.mem_i_datain (dma_data),
.mem_i_rdclock (avl_clk),
.mem_i_rdaddress (avl_mem_raddr),
.mem_o_dataout (avl_data_s));
.mem_i_wrclock_clk (dma_clk),
.mem_i_wren_wren (dma_mem_wea_s),
.mem_i_wraddress_wraddress (dma_mem_waddr),
.mem_i_datain_datain (dma_data),
.mem_i_rdclock_clk (avl_clk),
.mem_i_rdaddress_rdaddress (avl_mem_raddr),
.mem_o_dataout_dataout (avl_data_s));
// the fifo reset is the dma_xfer_req

14
library/intel/avl_dacfifo/util_dacfifo_bypass.v
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@ -110,13 +110,13 @@ module util_dacfifo_bypass #(
// An asymmetric memory to transfer data from DMAC interface to DAC interface
ad_mem_asym_bypass i_mem_asym (
.mem_i_wrclock (dma_clk),
.mem_i_wren (dma_mem_wea_s),
.mem_i_wraddress (dma_mem_waddr),
.mem_i_datain (dma_data),
.mem_i_rdclock (dac_clk),
.mem_i_rdaddress (dac_mem_raddr),
.mem_o_dataout (dac_mem_rdata_s));
.mem_i_wrclock_clk (dma_clk),
.mem_i_wren_wren (dma_mem_wea_s),
.mem_i_wraddress_wraddress (dma_mem_waddr),
.mem_i_datain_datain (dma_data),
.mem_i_rdclock_clk (dac_clk),
.mem_i_rdaddress_rdaddress (dac_mem_raddr),
.mem_o_dataout_dataout (dac_mem_rdata_s));
// dma reset is brought from dac domain

19
library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl
View File

@ -41,9 +41,20 @@ proc p_intel_mem_asym {} {
set_instance_parameter_value intel_mem {GUI_RAM_BLOCK_TYPE} {M20K}
set_instance_parameter_value intel_mem {GUI_CLOCK_TYPE} 1
add_interface mem_i conduit end
add_interface mem_o conduit end
set_interface_property mem_i EXPORT_OF intel_mem.ram_input
set_interface_property mem_o EXPORT_OF intel_mem.ram_output
add_interface mem_i_wrclock clock end
add_interface mem_i_wren conduit end
add_interface mem_i_wraddress conduit end
add_interface mem_i_datain conduit end
add_interface mem_i_rdclock clock end
add_interface mem_i_rdaddress conduit end
add_interface mem_o_dataout conduit end
set_interface_property mem_i_wrclock EXPORT_OF intel_mem.wrclock
set_interface_property mem_i_wren EXPORT_OF intel_mem.wren
set_interface_property mem_i_wraddress EXPORT_OF intel_mem.wraddress
set_interface_property mem_i_datain EXPORT_OF intel_mem.data
set_interface_property mem_i_rdclock EXPORT_OF intel_mem.rdclock
set_interface_property mem_i_rdaddress EXPORT_OF intel_mem.rdaddress
set_interface_property mem_o_dataout EXPORT_OF intel_mem.q
}