diff --git a/projects/daq3/vcu118/Makefile b/projects/daq3/vcu118/Makefile new file mode 100644 index 000000000..1128dbfec --- /dev/null +++ b/projects/daq3/vcu118/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := daq3_vcu118 + +M_DEPS += ../common/daq3_spi.v +M_DEPS += ../common/daq3_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc +M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl + +LIB_DEPS += axi_ad9152 +LIB_DEPS += axi_ad9680 +LIB_DEPS += axi_dmac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/daq3/vcu118/system_bd.tcl b/projects/daq3/vcu118/system_bd.tcl new file mode 100644 index 000000000..dd55c1ac7 --- /dev/null +++ b/projects/daq3/vcu118/system_bd.tcl @@ -0,0 +1,36 @@ + +## FIFO depth is 4Mb - 250k samples +set adc_fifo_address_width 16 + +## FIFO depth is 4Mb - 250k samples +set dac_fifo_address_width 15 + + +source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source ../common/daq3_bd.tcl + +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG0 0x331C +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG1 0xD038 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG2 0xFC1 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG3 0x120 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG4 0x2 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG1_G3 0xD038 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_CFG2_G3 0xFC1 + +ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG0 0x3fe +ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG1 0x29 +ad_ip_parameter util_daq3_xcvr CONFIG.CPLL_CFG2 0x203 +ad_ip_parameter util_daq3_xcvr CONFIG.RX_CLK25_DIV 25 +ad_ip_parameter util_daq3_xcvr CONFIG.TX_CLK25_DIV 25 + +ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST true +ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC true +ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST true +ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC true + +set_property -dict [list CONFIG.ADVANCED_PROPERTIES { __view__ { clocking { SW0 { ASSOCIATED_CLK aclk1 } } }}] [get_bd_cells axi_mem_interconnect] + diff --git a/projects/daq3/vcu118/system_constr.xdc b/projects/daq3/vcu118/system_constr.xdc new file mode 100644 index 000000000..fcb202ac2 --- /dev/null +++ b/projects/daq3/vcu118/system_constr.xdc @@ -0,0 +1,61 @@ + +# daq3 + +set_property -dict {PACKAGE_PIN AK38} [get_ports tx_ref_clk_p] ; ## D04 FMCP_HSPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AK39} [get_ports tx_ref_clk_n] ; ## D05 FMCP_HSPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AM38} [get_ports rx_ref_clk_p] ; ## B20 FMCP_HSPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AM39} [get_ports rx_ref_clk_n] ; ## B21 FMCP_HSPC_GBTCLK1_M2C_N + +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMCP_HSPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AL31 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMCP_HSPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_p] ; ## G09 FMCP_HSPC_LA03_P +set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx_sysref_n] ; ## G10 FMCP_HSPC_LA03_N +set_property -dict {PACKAGE_PIN AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_p] ; ## H07 FMCP_HSPC_LA02_P +set_property -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_n] ; ## H08 FMCP_HSPC_LA02_N +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_p] ; ## H10 FMCP_HSPC_LA04_P +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sysref_n] ; ## H11 FMCP_HSPC_LA04_N + +set_property -dict {PACKAGE_PIN AP38 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMCP_HSPC_LA05_P +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMCP_HSPC_LA10_P +set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMCP_HSPC_LA09_N +set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMCP_HSPC_LA05_N +set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMCP_HSPC_LA09_P +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## C11 FMCP_HSPC_LA06_N + +set_property -dict {PACKAGE_PIN AJ35 IOSTANDARD LVDS} [get_ports sysref_p] ; ## D17 FMCP_HSPC_LA13_P +set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVDS} [get_ports sysref_n] ; ## D18 FMCP_HSPC_LA13_N +set_property -dict {PACKAGE_PIN AH34 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMCP_HSPC_LA12_N +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMCP_HSPC_LA06_P + +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## G12 FMCP_HSPC_LA08_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## G13 FMCP_HSPC_LA08_N +set_property -dict {PACKAGE_PIN AH33 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMCP_HSPC_LA12_P +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMCP_HSPC_LA11_P +set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMCP_HSPC_LA11_N + +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMCP_HSPC_LA07_P +set_property -dict {PACKAGE_PIN AP37 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMCP_HSPC_LA07_N + +set_property -dict {PACKAGE_PIN AJ45} [get_ports rx_data_p[0]] ; ## A10 FMCP_HSPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AJ46} [get_ports rx_data_n[0]] ; ## A11 FMCP_HSPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AR45} [get_ports rx_data_p[1]] ; ## C06 FMCP_HSPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AR46} [get_ports rx_data_n[1]] ; ## C07 FMCP_HSPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AL45} [get_ports rx_data_p[2]] ; ## A06 FMCP_HSPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AL46} [get_ports rx_data_n[2]] ; ## A07 FMCP_HSPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AN45} [get_ports rx_data_p[3]] ; ## A02 FMCP_HSPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AN46} [get_ports rx_data_n[3]] ; ## A03 FMCP_HSPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AL40} [get_ports tx_data_p[0]] ; ## A30 FMCP_HSPC_DP3_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AL41} [get_ports tx_data_n[0]] ; ## A31 FMCP_HSPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AT42} [get_ports tx_data_p[1]] ; ## C02 FMCP_HSPC_DP0_C2M_P (tx_data_p[3]) +set_property -dict {PACKAGE_PIN AT43} [get_ports tx_data_n[1]] ; ## C03 FMCP_HSPC_DP0_C2M_N (tx_data_n[3]) +set_property -dict {PACKAGE_PIN AM42} [get_ports tx_data_p[2]] ; ## A26 FMCP_HSPC_DP2_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AM43} [get_ports tx_data_n[2]] ; ## A27 FMCP_HSPC_DP2_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AP42} [get_ports tx_data_p[3]] ; ## A22 FMCP_HSPC_DP1_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AP43} [get_ports tx_data_n[3]] ; ## A23 FMCP_HSPC_DP1_C2M_N (tx_data_n[2]) + +## clocks +create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtye4_channel/RXOUTCLK] + diff --git a/projects/daq3/vcu118/system_project.tcl b/projects/daq3/vcu118/system_project.tcl new file mode 100644 index 000000000..a1cdfdec9 --- /dev/null +++ b/projects/daq3/vcu118/system_project.tcl @@ -0,0 +1,18 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx daq3_vcu118 +adi_project_files daq3_vcu118 [list \ + "../common/daq3_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] + +## To improve timing in DDR4 MIG +set_property strategy Performance_Retiming [get_runs impl_1] + +adi_project_run daq3_vcu118 + diff --git a/projects/daq3/vcu118/system_top.v b/projects/daq3/vcu118/system_top.v new file mode 100644 index 000000000..f49378dc2 --- /dev/null +++ b/projects/daq3/vcu118/system_top.v @@ -0,0 +1,288 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + + input trig_p, + input trig_n, + + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, + + inout adc_pd, + inout dac_txen, + output sysref_p, + output sysref_n, + + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 7:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire trig; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + + assign iic_rstn = 1'b1; + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE4 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE4 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq3_spi i_spi ( + .spi_csn (spi_csn[2:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + OBUFDS i_obufds_sysref ( + .I (gpio_o[40]), + .O (sysref_p), + .OB (sysref_n)); + + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign gpio_i[39] = trig; + + ad_iobuf #(.DATA_WIDTH(7)) i_iobuf ( + .dio_t (gpio_t[38:32]), + .dio_i (gpio_o[38:32]), + .dio_o (gpio_i[38:32]), + .dio_p ({ adc_pd, // 38 + dac_txen, // 37 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status})); // 33-32 + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign gpio_i[63:40] = gpio_o[63:40]; + assign gpio_i[31:17] = gpio_o[31:17]; + + system_wrapper i_system_wrapper ( + .ddr4_act_n (ddr4_act_n), + .ddr4_adr (ddr4_addr), + .ddr4_ba (ddr4_ba), + .ddr4_bg (ddr4_bg), + .ddr4_ck_c (ddr4_ck_n), + .ddr4_ck_t (ddr4_ck_p), + .ddr4_cke (ddr4_cke), + .ddr4_cs_n (ddr4_cs_n), + .ddr4_dm_n (ddr4_dm_n), + .ddr4_dq (ddr4_dq), + .ddr4_dqs_c (ddr4_dqs_n), + .ddr4_dqs_t (ddr4_dqs_p), + .ddr4_odt (ddr4_odt), + .ddr4_reset_n (ddr4_reset_n), + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .sgmii_phyclk_clk_n (phy_clk_n), + .sgmii_phyclk_clk_p (phy_clk_p), + .phy_rst_n (phy_rst_n), + .phy_sd (1'b1), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref), + .uart_sin (uart_sin), + .uart_sout (uart_sout)); + +endmodule + +// *************************************************************************** +// ***************************************************************************