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usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism

main
Adrian Costina 2015-08-19 10:12:24 +03:00
parent 50d1a6dcca
commit f5de5ca487
2 changed files with 4 additions and 2 deletions
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4
library/axi_ad9671/axi_ad9671_if.v
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@ -201,12 +201,12 @@ module axi_ad9671_if (
adc_raddr_out <= 4'h8;
adc_sync_status <= 1'b0;
end else begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1;
end
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin

2
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -66,6 +66,8 @@ set_property -dict [list CONFIG.PCORE_ID {3}] $axi_ad9671_core_3
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd
set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ] $axi_usdrx1_jesd
set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] [get_bd_cells axi_usdrx1_gt]