From f5b5bbfbcae3146e40aee12eda3252e417a61c89 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 25 Sep 2015 17:57:40 +0300 Subject: [PATCH] fmcomms7: Update to the new JESD framework Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path. --- projects/fmcomms7/common/fmcomms7_bd.tcl | 322 ++++++++++------------- projects/fmcomms7/zc706/system_bd.tcl | 2 + projects/fmcomms7/zc706/system_top.v | 169 ------------ 3 files changed, 145 insertions(+), 348 deletions(-) diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index 8286f2086..e0175ccdc 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -13,33 +13,6 @@ create_bd_port -dir I tx_sysref create_bd_port -dir O -from 7 -to 0 tx_data_p create_bd_port -dir O -from 7 -to 0 tx_data_n -create_bd_port -dir O dac_clk -create_bd_port -dir O dac_valid_0 -create_bd_port -dir O dac_enable_0 -create_bd_port -dir I -from 63 -to 0 dac_ddata_0 -create_bd_port -dir O dac_valid_1 -create_bd_port -dir O dac_enable_1 -create_bd_port -dir I -from 63 -to 0 dac_ddata_1 -create_bd_port -dir O dac_valid_2 -create_bd_port -dir O dac_enable_2 -create_bd_port -dir I -from 63 -to 0 dac_ddata_2 -create_bd_port -dir O dac_valid_3 -create_bd_port -dir O dac_enable_3 -create_bd_port -dir I -from 63 -to 0 dac_ddata_3 -create_bd_port -dir I dac_drd -create_bd_port -dir O -from 255 -to 0 dac_ddata - -create_bd_port -dir O adc_clk -create_bd_port -dir O adc_enable_0 -create_bd_port -dir O adc_valid_0 -create_bd_port -dir O -from 63 -to 0 adc_data_0 -create_bd_port -dir O adc_enable_1 -create_bd_port -dir O adc_valid_1 -create_bd_port -dir O -from 63 -to 0 adc_data_1 -create_bd_port -dir I adc_dwr -create_bd_port -dir I adc_dsync -create_bd_port -dir I -from 127 -to 0 adc_ddata - create_bd_port -dir O -from 11 -to 0 spi2_csn_o create_bd_port -dir I -from 11 -to 0 spi2_csn_i create_bd_port -dir I spi2_clk_i @@ -59,7 +32,7 @@ set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9144_jesd set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9144_dma -set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9144_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9144_dma set_property -dict [list CONFIG.ID {1}] $axi_ad9144_dma set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma @@ -69,40 +42,57 @@ set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9144_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma +set axi_ad9144_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9144_upack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9144_upack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9144_upack + # adc peripherals set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] -set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9680_jesd] +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma + +set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack] +set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $axi_ad9680_cpack +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9680_cpack # dac/adc common gt set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt] -set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {8}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {5}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {6}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {7}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_4 {2}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_5 {0}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_6 {1}] $axi_fmcomms7_gt -set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_7 {4}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_0 {5}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_1 {3}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_2 {6}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_3 {7}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_4 {2}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_5 {0}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_6 {1}] $axi_fmcomms7_gt +set_property -dict [list CONFIG.TX_DATA_SEL_7 {4}] $axi_fmcomms7_gt + +set util_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcomms7_gt] +set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcomms7_gt +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcomms7_gt +set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcomms7_gt +set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcomms7_gt +set_property -dict [list CONFIG.TX_ENABLE {1}] $util_fmcomms7_gt +set_property -dict [list CONFIG.TX_NUM_OF_LANES {8}] $util_fmcomms7_gt set axi_fmcomms7_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_fmcomms7_spi] set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms7_spi @@ -122,143 +112,116 @@ ad_connect sys_cpu_clk axi_fmcomms7_spi/ext_spi_clk # connections (gt) -ad_connect axi_fmcomms7_gt/ref_clk_q rx_ref_clk -ad_connect axi_fmcomms7_gt/ref_clk_c tx_ref_clk -ad_connect axi_fmcomms7_gt/rx_data_p rx_data_p -ad_connect axi_fmcomms7_gt/rx_data_n rx_data_n -ad_connect axi_fmcomms7_gt/rx_sync rx_sync -ad_connect axi_fmcomms7_gt/rx_ext_sysref rx_sysref -ad_connect axi_fmcomms7_gt/tx_data_p tx_data_p -ad_connect axi_fmcomms7_gt/tx_data_n tx_data_n -ad_connect axi_fmcomms7_gt/tx_sync tx_sync -ad_connect axi_fmcomms7_gt/tx_ext_sysref tx_sysref +ad_connect util_fmcomms7_gt/qpll_ref_clk rx_ref_clk +ad_connect util_fmcomms7_gt/cpll_ref_clk tx_ref_clk + +ad_connect axi_fmcomms7_gt/gt_qpll_0 util_fmcomms7_gt/gt_qpll_0 +ad_connect axi_fmcomms7_gt/gt_pll_0 util_fmcomms7_gt/gt_pll_0 +ad_connect axi_fmcomms7_gt/gt_pll_1 util_fmcomms7_gt/gt_pll_1 +ad_connect axi_fmcomms7_gt/gt_pll_2 util_fmcomms7_gt/gt_pll_2 +ad_connect axi_fmcomms7_gt/gt_pll_3 util_fmcomms7_gt/gt_pll_3 +ad_connect axi_fmcomms7_gt/gt_pll_4 util_fmcomms7_gt/gt_pll_4 +ad_connect axi_fmcomms7_gt/gt_pll_5 util_fmcomms7_gt/gt_pll_5 +ad_connect axi_fmcomms7_gt/gt_pll_6 util_fmcomms7_gt/gt_pll_6 +ad_connect axi_fmcomms7_gt/gt_pll_7 util_fmcomms7_gt/gt_pll_7 +ad_connect axi_fmcomms7_gt/gt_rx_0 util_fmcomms7_gt/gt_rx_0 +ad_connect axi_fmcomms7_gt/gt_rx_1 util_fmcomms7_gt/gt_rx_1 +ad_connect axi_fmcomms7_gt/gt_rx_2 util_fmcomms7_gt/gt_rx_2 +ad_connect axi_fmcomms7_gt/gt_rx_3 util_fmcomms7_gt/gt_rx_3 +ad_connect axi_fmcomms7_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx +ad_connect axi_fmcomms7_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx +ad_connect axi_fmcomms7_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx +ad_connect axi_fmcomms7_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx +ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_fmcomms7_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out +ad_connect axi_fmcomms7_gt/gt_tx_0 util_fmcomms7_gt/gt_tx_0 +ad_connect axi_fmcomms7_gt/gt_tx_1 util_fmcomms7_gt/gt_tx_1 +ad_connect axi_fmcomms7_gt/gt_tx_2 util_fmcomms7_gt/gt_tx_2 +ad_connect axi_fmcomms7_gt/gt_tx_3 util_fmcomms7_gt/gt_tx_3 +ad_connect axi_fmcomms7_gt/gt_tx_4 util_fmcomms7_gt/gt_tx_4 +ad_connect axi_fmcomms7_gt/gt_tx_5 util_fmcomms7_gt/gt_tx_5 +ad_connect axi_fmcomms7_gt/gt_tx_6 util_fmcomms7_gt/gt_tx_6 +ad_connect axi_fmcomms7_gt/gt_tx_7 util_fmcomms7_gt/gt_tx_7 +ad_connect axi_fmcomms7_gt/gt_tx_ip_0 axi_ad9144_jesd/gt0_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_1 axi_ad9144_jesd/gt1_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_2 axi_ad9144_jesd/gt2_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_3 axi_ad9144_jesd/gt3_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_4 axi_ad9144_jesd/gt4_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_5 axi_ad9144_jesd/gt5_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_6 axi_ad9144_jesd/gt6_tx +ad_connect axi_fmcomms7_gt/gt_tx_ip_7 axi_ad9144_jesd/gt7_tx # connections (dac) -ad_connect axi_fmcomms7_gt/tx_clk_g dac_clk -ad_connect axi_fmcomms7_gt/tx_clk_g axi_fmcomms7_gt/tx_clk -ad_connect axi_fmcomms7_gt/tx_clk_g axi_ad9144_core/tx_clk -ad_connect axi_fmcomms7_gt/tx_clk_g axi_ad9144_jesd/tx_core_clk -ad_connect axi_fmcomms7_gt/tx_rst axi_ad9144_jesd/tx_reset -ad_connect axi_fmcomms7_gt/tx_sysref axi_ad9144_jesd/tx_sysref - -create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_charisk -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_ccat_tx_gt_charisk] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_ccat_tx_gt_charisk] - -ad_connect util_ccat_tx_gt_charisk/ccat_data axi_fmcomms7_gt/tx_gt_charisk -ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9144_jesd/gt0_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9144_jesd/gt1_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9144_jesd/gt2_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9144_jesd/gt3_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_4 axi_ad9144_jesd/gt4_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_5 axi_ad9144_jesd/gt5_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_6 axi_ad9144_jesd/gt6_txcharisk -ad_connect util_ccat_tx_gt_charisk/data_7 axi_ad9144_jesd/gt7_txcharisk - -create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_data -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_ccat_tx_gt_data] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_ccat_tx_gt_data] - -ad_connect util_ccat_tx_gt_data/ccat_data axi_fmcomms7_gt/tx_gt_data -ad_connect util_ccat_tx_gt_data/data_0 axi_ad9144_jesd/gt0_txdata -ad_connect util_ccat_tx_gt_data/data_1 axi_ad9144_jesd/gt1_txdata -ad_connect util_ccat_tx_gt_data/data_2 axi_ad9144_jesd/gt2_txdata -ad_connect util_ccat_tx_gt_data/data_3 axi_ad9144_jesd/gt3_txdata -ad_connect util_ccat_tx_gt_data/data_4 axi_ad9144_jesd/gt4_txdata -ad_connect util_ccat_tx_gt_data/data_5 axi_ad9144_jesd/gt5_txdata -ad_connect util_ccat_tx_gt_data/data_6 axi_ad9144_jesd/gt6_txdata -ad_connect util_ccat_tx_gt_data/data_7 axi_ad9144_jesd/gt7_txdata - -ad_connect axi_fmcomms7_gt/tx_rst_done axi_ad9144_jesd/tx_reset_done -ad_connect axi_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync -ad_connect axi_fmcomms7_gt/tx_ip_sof axi_ad9144_jesd/tx_start_of_frame -ad_connect axi_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata -ad_connect axi_fmcomms7_gt/tx_data axi_ad9144_core/tx_data -ad_connect axi_ad9144_core/dac_clk axi_ad9144_dma/fifo_rd_clk -ad_connect axi_ad9144_core/dac_valid_0 dac_valid_0 -ad_connect axi_ad9144_core/dac_enable_0 dac_enable_0 -ad_connect axi_ad9144_core/dac_ddata_0 dac_ddata_0 -ad_connect axi_ad9144_core/dac_valid_1 dac_valid_1 -ad_connect axi_ad9144_core/dac_enable_1 dac_enable_1 -ad_connect axi_ad9144_core/dac_ddata_1 dac_ddata_1 -ad_connect axi_ad9144_core/dac_valid_2 dac_valid_2 -ad_connect axi_ad9144_core/dac_enable_2 dac_enable_2 -ad_connect axi_ad9144_core/dac_ddata_2 dac_ddata_2 -ad_connect axi_ad9144_core/dac_valid_3 dac_valid_3 -ad_connect axi_ad9144_core/dac_enable_3 dac_enable_3 -ad_connect axi_ad9144_core/dac_ddata_3 dac_ddata_3 -ad_connect dac_drd axi_ad9144_dma/fifo_rd_en -ad_connect dac_ddata axi_ad9144_dma/fifo_rd_dout -ad_connect axi_ad9144_core/dac_dunf axi_ad9144_dma/fifo_rd_underflow +ad_connect util_fmcomms7_gt/tx_sysref tx_sysref +ad_connect util_fmcomms7_gt/tx_p tx_data_p +ad_connect util_fmcomms7_gt/tx_n tx_data_n +ad_connect util_fmcomms7_gt/tx_sync tx_sync +ad_connect util_fmcomms7_gt/tx_out_clk util_fmcomms7_gt/tx_clk +ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_jesd/tx_core_clk +ad_connect util_fmcomms7_gt/tx_ip_rst axi_ad9144_jesd/tx_reset +ad_connect util_fmcomms7_gt/tx_ip_rst_done axi_ad9144_jesd/tx_reset_done +ad_connect util_fmcomms7_gt/tx_ip_sysref axi_ad9144_jesd/tx_sysref +ad_connect util_fmcomms7_gt/tx_ip_sync axi_ad9144_jesd/tx_sync +ad_connect util_fmcomms7_gt/tx_ip_data axi_ad9144_jesd/tx_tdata +ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_core/tx_clk +ad_connect util_fmcomms7_gt/tx_data axi_ad9144_core/tx_data +ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_upack/dac_clk +ad_connect axi_ad9144_core/dac_enable_0 axi_ad9144_upack/dac_enable_0 +ad_connect axi_ad9144_core/dac_ddata_0 axi_ad9144_upack/dac_data_0 +ad_connect axi_ad9144_core/dac_valid_0 axi_ad9144_upack/dac_valid_0 +ad_connect axi_ad9144_core/dac_enable_1 axi_ad9144_upack/dac_enable_1 +ad_connect axi_ad9144_core/dac_ddata_1 axi_ad9144_upack/dac_data_1 +ad_connect axi_ad9144_core/dac_valid_1 axi_ad9144_upack/dac_valid_1 +ad_connect axi_ad9144_core/dac_enable_2 axi_ad9144_upack/dac_enable_2 +ad_connect axi_ad9144_core/dac_ddata_2 axi_ad9144_upack/dac_data_2 +ad_connect axi_ad9144_core/dac_valid_2 axi_ad9144_upack/dac_valid_2 +ad_connect axi_ad9144_core/dac_enable_3 axi_ad9144_upack/dac_enable_3 +ad_connect axi_ad9144_core/dac_ddata_3 axi_ad9144_upack/dac_data_3 +ad_connect axi_ad9144_core/dac_valid_3 axi_ad9144_upack/dac_valid_3 +ad_connect util_fmcomms7_gt/tx_out_clk axi_ad9144_fifo/dac_clk +ad_connect axi_ad9144_upack/dac_valid axi_ad9144_fifo/dac_valid +ad_connect axi_ad9144_upack/dac_data axi_ad9144_fifo/dac_data +ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk +ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst +ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn +ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req +ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready +ad_connect axi_ad9144_fifo/dma_data axi_ad9144_dma/m_axis_data +ad_connect axi_ad9144_fifo/dma_valid axi_ad9144_dma/m_axis_valid +ad_connect axi_ad9144_fifo/dma_xfer_last axi_ad9144_dma/m_axis_last # connections (adc) -ad_connect axi_fmcomms7_gt/rx_clk_g adc_clk -ad_connect axi_fmcomms7_gt/rx_clk_g axi_fmcomms7_gt/rx_clk -ad_connect axi_fmcomms7_gt/rx_clk_g axi_ad9680_core/rx_clk -ad_connect axi_fmcomms7_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk -ad_connect axi_fmcomms7_gt/rx_rst axi_ad9680_jesd/rx_reset -ad_connect axi_fmcomms7_gt/rx_sysref axi_ad9680_jesd/rx_sysref - -create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_charisk] - -ad_connect util_bsplit_rx_gt_charisk/data axi_fmcomms7_gt/rx_gt_charisk -ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk -ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9680_jesd/gt1_rxcharisk -ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9680_jesd/gt2_rxcharisk -ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9680_jesd/gt3_rxcharisk - -create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_disperr] - -ad_connect util_bsplit_rx_gt_disperr/data axi_fmcomms7_gt/rx_gt_disperr -ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr -ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9680_jesd/gt1_rxdisperr -ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9680_jesd/gt2_rxdisperr -ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9680_jesd/gt3_rxdisperr - -create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_notintable] - -ad_connect util_bsplit_rx_gt_notintable/data axi_fmcomms7_gt/rx_gt_notintable -ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable -ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9680_jesd/gt1_rxnotintable -ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9680_jesd/gt2_rxnotintable -ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9680_jesd/gt3_rxnotintable - -create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data -set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] [get_bd_cells util_bsplit_rx_gt_data] - -ad_connect util_bsplit_rx_gt_data/data axi_fmcomms7_gt/rx_gt_data -ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata -ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9680_jesd/gt1_rxdata -ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9680_jesd/gt2_rxdata -ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9680_jesd/gt3_rxdata - -ad_connect axi_fmcomms7_gt/rx_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect axi_fmcomms7_gt/rx_ip_comma_align axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect axi_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect axi_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect axi_fmcomms7_gt/rx_data axi_ad9680_core/rx_data -ad_connect axi_ad9680_core/adc_enable_0 adc_enable_0 -ad_connect axi_ad9680_core/adc_valid_0 adc_valid_0 -ad_connect axi_ad9680_core/adc_data_0 adc_data_0 -ad_connect axi_ad9680_core/adc_enable_1 adc_enable_1 -ad_connect axi_ad9680_core/adc_valid_1 adc_valid_1 -ad_connect axi_ad9680_core/adc_data_1 adc_data_1 -ad_connect axi_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst -ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk -ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf -ad_connect adc_dwr axi_ad9680_fifo/adc_wr -ad_connect adc_ddata axi_ad9680_fifo/adc_wdata +ad_connect util_fmcomms7_gt/rx_sysref rx_sysref +ad_connect util_fmcomms7_gt/rx_p rx_data_p +ad_connect util_fmcomms7_gt/rx_n rx_data_n +ad_connect util_fmcomms7_gt/rx_sync rx_sync +ad_connect util_fmcomms7_gt/rx_out_clk util_fmcomms7_gt/rx_clk +ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk +ad_connect util_fmcomms7_gt/rx_ip_rst axi_ad9680_jesd/rx_reset +ad_connect util_fmcomms7_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done +ad_connect util_fmcomms7_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref +ad_connect util_fmcomms7_gt/rx_ip_sync axi_ad9680_jesd/rx_sync +ad_connect util_fmcomms7_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame +ad_connect util_fmcomms7_gt/rx_ip_data axi_ad9680_jesd/rx_tdata +ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_core/rx_clk +ad_connect util_fmcomms7_gt/rx_data axi_ad9680_core/rx_data +ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_cpack/adc_clk +ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_cpack/adc_rst +ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0 +ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0 +ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0 +ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1 +ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1 +ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1 +ad_connect util_fmcomms7_gt/rx_out_clk axi_ad9680_fifo/adc_clk +ad_connect util_fmcomms7_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr +ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn @@ -266,6 +229,7 @@ ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req +ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf # interconnect (cpu) diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl index 1e93f6e1e..3206d6a58 100644 --- a/projects/fmcomms7/zc706/system_bd.tcl +++ b/projects/fmcomms7/zc706/system_bd.tcl @@ -1,8 +1,10 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10 create_bd_port -dir I -type rst sys_rst create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index 90c17d789..3dffcd50b 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -311,150 +311,6 @@ module system_top ( wire tx_sync0; wire tx_sync1; wire tx_sync; - wire dac_clk; - wire [255:0] dac_ddata; - wire dac_enable_0; - wire dac_enable_1; - wire dac_enable_2; - wire dac_enable_3; - wire dac_valid_0; - wire dac_valid_1; - wire dac_valid_2; - wire dac_valid_3; - wire adc_clk; - wire [ 63:0] adc_data_0; - wire [ 63:0] adc_data_1; - wire adc_enable_0; - wire adc_enable_1; - wire adc_valid_0; - wire adc_valid_1; - - // adc-dac data - - always @(posedge dac_clk) begin - case ({dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0}) - 4'b1111: begin - dac_drd <= dac_valid_0 & dac_valid_1 & dac_valid_2 & dac_valid_3; - dac_ddata_0[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)]; - dac_ddata_1[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)]; - dac_ddata_2[15: 0] <= dac_ddata[((16* 2)+15):(16* 2)]; - dac_ddata_3[15: 0] <= dac_ddata[((16* 3)+15):(16* 3)]; - dac_ddata_0[31:16] <= dac_ddata[((16* 4)+15):(16* 4)]; - dac_ddata_1[31:16] <= dac_ddata[((16* 5)+15):(16* 5)]; - dac_ddata_2[31:16] <= dac_ddata[((16* 6)+15):(16* 6)]; - dac_ddata_3[31:16] <= dac_ddata[((16* 7)+15):(16* 7)]; - dac_ddata_0[47:32] <= dac_ddata[((16* 8)+15):(16* 8)]; - dac_ddata_1[47:32] <= dac_ddata[((16* 9)+15):(16* 9)]; - dac_ddata_2[47:32] <= dac_ddata[((16*10)+15):(16*10)]; - dac_ddata_3[47:32] <= dac_ddata[((16*11)+15):(16*11)]; - dac_ddata_0[63:48] <= dac_ddata[((16*12)+15):(16*12)]; - dac_ddata_1[63:48] <= dac_ddata[((16*13)+15):(16*13)]; - dac_ddata_2[63:48] <= dac_ddata[((16*14)+15):(16*14)]; - dac_ddata_3[63:48] <= dac_ddata[((16*15)+15):(16*15)]; - end - 4'b1100: begin - dac_drd <= dac_valid_2 & dac_valid_3 & ~dac_drd; - dac_ddata_0 <= 64'd0; - dac_ddata_1 <= 64'd0; - if (dac_drd == 1'b1) begin - dac_ddata_2[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)]; - dac_ddata_3[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)]; - dac_ddata_2[31:16] <= dac_ddata[((16* 2)+15):(16* 2)]; - dac_ddata_3[31:16] <= dac_ddata[((16* 3)+15):(16* 3)]; - dac_ddata_2[47:32] <= dac_ddata[((16* 4)+15):(16* 4)]; - dac_ddata_3[47:32] <= dac_ddata[((16* 5)+15):(16* 5)]; - dac_ddata_2[63:48] <= dac_ddata[((16* 6)+15):(16* 6)]; - dac_ddata_3[63:48] <= dac_ddata[((16* 7)+15):(16* 7)]; - end else begin - dac_ddata_2[15: 0] <= dac_ddata[((16* 8)+15):(16* 8)]; - dac_ddata_3[15: 0] <= dac_ddata[((16* 9)+15):(16* 9)]; - dac_ddata_2[31:16] <= dac_ddata[((16*10)+15):(16*10)]; - dac_ddata_3[31:16] <= dac_ddata[((16*11)+15):(16*11)]; - dac_ddata_2[47:32] <= dac_ddata[((16*12)+15):(16*12)]; - dac_ddata_3[47:32] <= dac_ddata[((16*13)+15):(16*13)]; - dac_ddata_2[63:48] <= dac_ddata[((16*14)+15):(16*14)]; - dac_ddata_3[63:48] <= dac_ddata[((16*15)+15):(16*15)]; - end - end - 4'b0011: begin - dac_drd <= dac_valid_0 & dac_valid_1 & ~dac_drd; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - if (dac_drd == 1'b1) begin - dac_ddata_0[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)]; - dac_ddata_1[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)]; - dac_ddata_0[31:16] <= dac_ddata[((16* 2)+15):(16* 2)]; - dac_ddata_1[31:16] <= dac_ddata[((16* 3)+15):(16* 3)]; - dac_ddata_0[47:32] <= dac_ddata[((16* 4)+15):(16* 4)]; - dac_ddata_1[47:32] <= dac_ddata[((16* 5)+15):(16* 5)]; - dac_ddata_0[63:48] <= dac_ddata[((16* 6)+15):(16* 6)]; - dac_ddata_1[63:48] <= dac_ddata[((16* 7)+15):(16* 7)]; - end else begin - dac_ddata_0[15: 0] <= dac_ddata[((16* 8)+15):(16* 8)]; - dac_ddata_1[15: 0] <= dac_ddata[((16* 9)+15):(16* 9)]; - dac_ddata_0[31:16] <= dac_ddata[((16*10)+15):(16*10)]; - dac_ddata_1[31:16] <= dac_ddata[((16*11)+15):(16*11)]; - dac_ddata_0[47:32] <= dac_ddata[((16*12)+15):(16*12)]; - dac_ddata_1[47:32] <= dac_ddata[((16*13)+15):(16*13)]; - dac_ddata_0[63:48] <= dac_ddata[((16*14)+15):(16*14)]; - dac_ddata_1[63:48] <= dac_ddata[((16*15)+15):(16*15)]; - end - end - default: begin - dac_drd <= 1'b0; - dac_ddata_0 <= 64'd0; - dac_ddata_1 <= 64'd0; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - endcase - end - - always @(posedge adc_clk) begin - case ({adc_enable_1, adc_enable_0}) - 2'b11: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & adc_valid_0; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_0[63:48]; - adc_ddata[ 95: 80] <= adc_data_1[47:32]; - adc_ddata[ 79: 64] <= adc_data_0[47:32]; - adc_ddata[ 63: 48] <= adc_data_1[31:16]; - adc_ddata[ 47: 32] <= adc_data_0[31:16]; - adc_ddata[ 31: 16] <= adc_data_1[15: 0]; - adc_ddata[ 15: 0] <= adc_data_0[15: 0]; - end - 2'b10: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_1[47:32]; - adc_ddata[ 95: 80] <= adc_data_1[31:16]; - adc_ddata[ 79: 64] <= adc_data_1[15: 0]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - 2'b01: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_0 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_0[63:48]; - adc_ddata[111: 96] <= adc_data_0[47:32]; - adc_ddata[ 95: 80] <= adc_data_0[31:16]; - adc_ddata[ 79: 64] <= adc_data_0[15: 0]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - default: begin - adc_dsync <= 1'b0; - adc_dwr <= 1'b0; - adc_ddata <= 128'd0; - end - endcase - end // spi @@ -565,31 +421,6 @@ module system_top ( .dio_p (gpio_bd)); system_wrapper i_system_wrapper ( - .adc_clk (adc_clk), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_ddata (adc_ddata), - .adc_dsync (adc_dsync), - .adc_dwr (adc_dwr), - .adc_enable_0 (adc_enable_0), - .adc_enable_1 (adc_enable_1), - .adc_valid_0 (adc_valid_0), - .adc_valid_1 (adc_valid_1), - .dac_clk (dac_clk), - .dac_ddata (dac_ddata), - .dac_ddata_0 (dac_ddata_0), - .dac_ddata_1 (dac_ddata_1), - .dac_ddata_2 (dac_ddata_2), - .dac_ddata_3 (dac_ddata_3), - .dac_drd (dac_drd), - .dac_enable_0 (dac_enable_0), - .dac_enable_1 (dac_enable_1), - .dac_enable_2 (dac_enable_2), - .dac_enable_3 (dac_enable_3), - .dac_valid_0 (dac_valid_0), - .dac_valid_1 (dac_valid_1), - .dac_valid_2 (dac_valid_2), - .dac_valid_3 (dac_valid_3), .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n),