axi_logic_analyzer: equalize delay paths
- Add parameter for input data delay time to easily match the one of the adc_trigger. - Change the trigger delay path to match between the internal and external(adc_trigger delays).main
AndreiGrozav
AndreiGrozav
parent
5e08e2d548
commit
f5ac0f7019
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@ -35,7 +35,13 @@
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`timescale 1ns/100ps
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module axi_logic_analyzer (
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module axi_logic_analyzer #(
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// add sample delays on LA to compensate for adc path delay
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parameter ADC_PATH_DELAY = 19) (
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// interface
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input clk,
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output clk_out,
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@ -45,7 +51,7 @@ module axi_logic_analyzer (
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output [15:0] data_t,
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input [ 1:0] trigger_i,
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output reg adc_valid,
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output adc_valid,
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output [15:0] adc_data,
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input [15:0] dac_data,
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@ -83,7 +89,6 @@ module axi_logic_analyzer (
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// internal registers
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reg [15:0] data_m1 = 'd0;
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reg [15:0] data_r = 'd0;
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reg [ 1:0] trigger_m1 = 'd0;
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reg [31:0] downsampler_counter_la = 'd0;
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@ -107,7 +112,7 @@ module axi_logic_analyzer (
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reg streaming_on;
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reg [15:0] adc_data_m2 = 'd0;
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reg [15:0] adc_data_mn = 'd0;
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// internal signals
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@ -156,7 +161,7 @@ module axi_logic_analyzer (
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assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
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assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
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assign adc_data = adc_data_m2;
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assign adc_data = adc_data_mn;
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always @(posedge clk_out) begin
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if (trigger_delay == 0) begin
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@ -218,26 +223,38 @@ module axi_logic_analyzer (
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.I1 (data_i[0]),
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.S (clock_select));
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// synchronization
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// - synchronization
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// - compensate for m2k adc path delay
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// - transfer data at clock frequency if capture is enabled
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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data_m1 <= data_i;
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trigger_m1 <= trigger_i;
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genvar j;
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generate
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reg [15:0] data_m[ADC_PATH_DELAY-2:0];
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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data_m[0] <= data_i;
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end
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end
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end
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// transfer data at clock frequency
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// if capture is enabled
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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adc_data_m2 <= data_m1;
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adc_valid <= 1'b1;
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end else begin
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adc_valid <= 1'b0;
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for (j = 0; j < ADC_PATH_DELAY - 2; j = j + 1) begin
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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data_m[j+1] <= data_m[j];
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end
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end
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end
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end
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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adc_data_mn <= data_m[ADC_PATH_DELAY-2];
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end
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end
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endgenerate
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assign adc_valid = sample_valid_la;
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// downsampler logic analyzer
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@ -295,7 +312,7 @@ module axi_logic_analyzer (
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.clk (clk_out),
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.reset (reset),
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.data (adc_data_m2),
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.data (adc_data_mn),
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.data_valid(sample_valid_la),
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.trigger_i (trigger_m1),
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.trigger_in (trigger_in),
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@ -329,7 +346,7 @@ module axi_logic_analyzer (
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.clock_select (clock_select),
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.overwrite_enable (overwrite_enable),
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.overwrite_data (overwrite_data),
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.input_data (adc_data_m2),
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.input_data (adc_data_mn),
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.od_pp_n (od_pp_n),
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.triggered (up_triggered),
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@ -66,13 +66,11 @@ module axi_logic_analyzer_trigger (
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reg trigger_active;
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reg trigger_active_mux;
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reg trigger_active_d1;
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reg trigger_active_d2;
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always @(posedge clk) begin
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if (data_valid == 1'b1) begin
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trigger_active_d1 <= trigger_active_mux;
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trigger_active_d2 <= trigger_active_d1;
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trigger_out <= trigger_active_d2;
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trigger_out <= trigger_active_d1;
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trigger_out_adc <= trigger_active_mux;
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end
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end
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@ -82,20 +80,22 @@ module axi_logic_analyzer_trigger (
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// 0 OR
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// 1 AND
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always @(*) begin
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case (trigger_logic[0])
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0: trigger_active = |((edge_detect & edge_detect_enable) |
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(rise_edge & rise_edge_enable) |
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(fall_edge & fall_edge_enable) |
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(low_level & low_level_enable) |
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(high_level & high_level_enable));
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1: trigger_active = &((edge_detect | ~edge_detect_enable) &
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(rise_edge | ~rise_edge_enable) &
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(fall_edge | ~fall_edge_enable) &
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(low_level | ~low_level_enable) &
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(high_level | ~high_level_enable));
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default: trigger_active = 1'b1;
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endcase
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always @(posedge clk) begin
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if (data_valid == 1'b1) begin
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case (trigger_logic[0])
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0: trigger_active <= |((edge_detect & edge_detect_enable) |
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(rise_edge & rise_edge_enable) |
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(fall_edge & fall_edge_enable) |
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(low_level & low_level_enable) |
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(high_level & high_level_enable));
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1: trigger_active <= &((edge_detect | ~edge_detect_enable) &
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(rise_edge | ~rise_edge_enable) &
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(fall_edge | ~fall_edge_enable) &
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(low_level | ~low_level_enable) &
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(high_level | ~high_level_enable));
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default: trigger_active = 1'b1;
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endcase
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end
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end
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always @(*) begin
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