diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 29ddd95b9..c1f5d4a08 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -133,9 +133,6 @@ # Code owners for arradio folder /projects/arradio/ andrei.grozav@analog.com adrian.costina@analog.com -# Code owners for cn0501 folder -/projects/cn0501/ paul.pop@analog.com adrian.costina@analog.com - # Code owners for cn0506 folder /projects/cn0506/ alin-tudor.sferle@analog.com adrian.costina@analog.com diff --git a/projects/cn0501/Makefile b/projects/cn0501/Makefile deleted file mode 100644 index 1402069e1..000000000 --- a/projects/cn0501/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -include ../scripts/project-toplevel.mk diff --git a/projects/cn0501/Readme.md b/projects/cn0501/Readme.md deleted file mode 100755 index f22a656ba..000000000 --- a/projects/cn0501/Readme.md +++ /dev/null @@ -1,9 +0,0 @@ -# CN0501 HDL Project - -Here are some pointers to help you: - * [Board Product Page](https://www.analog.com/en/products/cn0501.html) - * Parts : [CN0501-geophone](https://www.analog.com/en/products/cn0501.html) - [8-Channel, 24-Bit, Simultaneous Sampling ADC | AD7768](https://www.analog.com/ad7768) - * Project Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501 - * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501 - * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7768 \ No newline at end of file diff --git a/projects/cn0501/common/cn0501_bd.tcl b/projects/cn0501/common/cn0501_bd.tcl deleted file mode 100644 index 4ad07ca07..000000000 --- a/projects/cn0501/common/cn0501_bd.tcl +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################### -## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ad7768 interface -create_bd_port -dir I clk_in -create_bd_port -dir I ready_in -create_bd_port -dir I -from 7 -to 0 data_in - -# adc(cn0501-dma) - -ad_ip_instance axi_dmac cn0501_dma -ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_SRC 2 -ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_DEST 0 -ad_ip_parameter cn0501_dma CONFIG.CYCLIC 0 -ad_ip_parameter cn0501_dma CONFIG.SYNC_TRANSFER_START 1 -ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_SRC 0 -ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter cn0501_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_SRC 256 -ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_DEST 64 - -# axi_ad77684 - -ad_ip_instance axi_ad7768 axi_ad7768_adc -ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8 - -# adc-path channel pack - -ad_ip_instance util_cpack2 cn0501_adc_pack -ad_ip_parameter cn0501_adc_pack CONFIG.NUM_OF_CHANNELS 8 -ad_ip_parameter cn0501_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32 - -# connections - -for {set i 0} {$i < 8} {incr i} { - ad_connect axi_ad7768_adc/adc_enable_$i cn0501_adc_pack/enable_$i - ad_connect axi_ad7768_adc/adc_data_$i cn0501_adc_pack/fifo_wr_data_$i -} - -ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0 -ad_connect axi_ad7768_adc/clk_in clk_in -ad_connect axi_ad7768_adc/ready_in ready_in -ad_connect axi_ad7768_adc/data_in data_in -ad_connect axi_ad7768_adc/adc_valid cn0501_adc_pack/fifo_wr_en -ad_connect axi_ad7768_adc/adc_clk cn0501_adc_pack/clk -ad_connect axi_ad7768_adc/adc_reset cn0501_adc_pack/reset -ad_connect axi_ad7768_adc/adc_dovf cn0501_adc_pack/fifo_wr_overflow - -ad_connect cn0501_dma/s_axi_aclk $sys_cpu_clk -ad_connect cn0501_dma/m_dest_axi_aresetn $sys_cpu_resetn -ad_connect cn0501_dma/m_dest_axi_aclk $sys_cpu_clk -ad_connect cn0501_dma/fifo_wr_clk axi_ad7768_adc/adc_clk -ad_connect cn0501_dma/fifo_wr cn0501_adc_pack/packed_fifo_wr - -# cpu / memory interconnects - -ad_cpu_interconnect 0x44a00000 axi_ad7768_adc -ad_cpu_interconnect 0x44a30000 cn0501_dma - -ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_cpu_clk cn0501_dma/m_dest_axi - -# interrupts - -ad_cpu_interrupt "ps-13" "mb-13" cn0501_dma/irq diff --git a/projects/cn0501/coraz7s/Makefile b/projects/cn0501/coraz7s/Makefile deleted file mode 100644 index 48aafdf7e..000000000 --- a/projects/cn0501/coraz7s/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := cn0501_coraz7s - -M_DEPS += ../common/cn0501_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl -M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc -M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_ad7768 -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 - -include ../../scripts/project-xilinx.mk diff --git a/projects/cn0501/coraz7s/system_bd.tcl b/projects/cn0501/coraz7s/system_bd.tcl deleted file mode 100644 index fcad89e10..000000000 --- a/projects/cn0501/coraz7s/system_bd.tcl +++ /dev/null @@ -1,18 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl -source ../common/cn0501_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -set sys_cstring "sys rom custom string placeholder" - -sysid_gen_sys_init_file $sys_cstring diff --git a/projects/cn0501/coraz7s/system_constr.xdc b/projects/cn0501/coraz7s/system_constr.xdc deleted file mode 100644 index c6c71c3df..000000000 --- a/projects/cn0501/coraz7s/system_constr.xdc +++ /dev/null @@ -1,30 +0,0 @@ -############################################################################### -## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - - set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in ]; ## P12.10 IO8 - set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in ]; ## P12.9 IO9 - - set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]]; ## P14.1 IO0 - set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]]; ## P14.2 IO1 - set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]]; ## P14.3 IO2 - set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]]; ## P14.4 IO3 - set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]]; ## P14.1 IO4 - set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]]; ## P14.2 IO5 - set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]]; ## P14.3 IO6 - set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]]; ## P14.4 IO7 - - set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn ]; ## P12.8 IO10 - set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11 - set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12 - set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13 - -set input_clock_period 31.25; # Period of input clock fMAX_DCLK=32MHz -set hold_time 8.5; -set setup_time 8.5; - -create_clock -name adc_clk -period $input_clock_period [get_ports clk_in] - -set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay; -set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay; diff --git a/projects/cn0501/coraz7s/system_project.tcl b/projects/cn0501/coraz7s/system_project.tcl deleted file mode 100644 index 13394ba71..000000000 --- a/projects/cn0501/coraz7s/system_project.tcl +++ /dev/null @@ -1,19 +0,0 @@ -############################################################################### -## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# load script -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project cn0501_coraz7s - -adi_project_files cn0501_coraz7s [list \ - "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "system_top.v" \ - "system_constr.xdc" ] - -adi_project_run cn0501_coraz7s diff --git a/projects/cn0501/coraz7s/system_top.v b/projects/cn0501/coraz7s/system_top.v deleted file mode 100644 index 93499068a..000000000 --- a/projects/cn0501/coraz7s/system_top.v +++ /dev/null @@ -1,149 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [ 1:0] btn, - inout [ 5:0] led, - - input clk_in, - input ready_in, - input [ 7:0] data_in, - - output spi_csn, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire [63:0] adc_gpio_i; - wire [63:0] adc_gpio_o; - wire [63:0] adc_gpio_t; - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_iobuf_buttons ( - .dio_t(gpio_t[1:0]), - .dio_i(gpio_o[1:0]), - .dio_o(gpio_i[1:0]), - .dio_p(btn)); - - ad_iobuf #( - .DATA_WIDTH(6) - ) i_iobuf_leds ( - .dio_t(gpio_t[7:2]), - .dio_i(gpio_o[7:2]), - .dio_o(gpio_i[7:2]), - .dio_p(led)); - - assign gpio_i[63:8] = gpio_o[63:8]; - - system_wrapper i_system_wrapper ( - .clk_in (clk_in), - .ready_in (ready_in), - .data_in (data_in), - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o ()); - -endmodule