projects/cn0501: Removed CN0501 project.
The CN0501 project was removed because the board development was canceled. Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>main
PopPaul2021
PopPaul2021
parent
91ec36f417
commit
f5184b4e14
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@ -133,9 +133,6 @@
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# Code owners for arradio folder
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/projects/arradio/ andrei.grozav@analog.com adrian.costina@analog.com
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# Code owners for cn0501 folder
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/projects/cn0501/ paul.pop@analog.com adrian.costina@analog.com
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# Code owners for cn0506 folder
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/projects/cn0506/ alin-tudor.sferle@analog.com adrian.costina@analog.com
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@ -1,7 +0,0 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -1,9 +0,0 @@
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# CN0501 HDL Project
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/en/products/cn0501.html)
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* Parts : [CN0501-geophone](https://www.analog.com/en/products/cn0501.html)
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[8-Channel, 24-Bit, Simultaneous Sampling ADC | AD7768](https://www.analog.com/ad7768)
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/cn0501
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7768
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@ -1,67 +0,0 @@
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###############################################################################
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## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# ad7768 interface
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create_bd_port -dir I clk_in
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create_bd_port -dir I ready_in
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create_bd_port -dir I -from 7 -to 0 data_in
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# adc(cn0501-dma)
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ad_ip_instance axi_dmac cn0501_dma
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ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter cn0501_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter cn0501_dma CONFIG.CYCLIC 0
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ad_ip_parameter cn0501_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter cn0501_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter cn0501_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_SRC 256
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ad_ip_parameter cn0501_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# axi_ad77684
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ad_ip_instance axi_ad7768 axi_ad7768_adc
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ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8
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# adc-path channel pack
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ad_ip_instance util_cpack2 cn0501_adc_pack
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ad_ip_parameter cn0501_adc_pack CONFIG.NUM_OF_CHANNELS 8
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ad_ip_parameter cn0501_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
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# connections
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for {set i 0} {$i < 8} {incr i} {
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ad_connect axi_ad7768_adc/adc_enable_$i cn0501_adc_pack/enable_$i
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ad_connect axi_ad7768_adc/adc_data_$i cn0501_adc_pack/fifo_wr_data_$i
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}
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ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0
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ad_connect axi_ad7768_adc/clk_in clk_in
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ad_connect axi_ad7768_adc/ready_in ready_in
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ad_connect axi_ad7768_adc/data_in data_in
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ad_connect axi_ad7768_adc/adc_valid cn0501_adc_pack/fifo_wr_en
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ad_connect axi_ad7768_adc/adc_clk cn0501_adc_pack/clk
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ad_connect axi_ad7768_adc/adc_reset cn0501_adc_pack/reset
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ad_connect axi_ad7768_adc/adc_dovf cn0501_adc_pack/fifo_wr_overflow
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ad_connect cn0501_dma/s_axi_aclk $sys_cpu_clk
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ad_connect cn0501_dma/m_dest_axi_aresetn $sys_cpu_resetn
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ad_connect cn0501_dma/m_dest_axi_aclk $sys_cpu_clk
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ad_connect cn0501_dma/fifo_wr_clk axi_ad7768_adc/adc_clk
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ad_connect cn0501_dma/fifo_wr cn0501_adc_pack/packed_fifo_wr
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# cpu / memory interconnects
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ad_cpu_interconnect 0x44a00000 axi_ad7768_adc
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ad_cpu_interconnect 0x44a30000 cn0501_dma
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk cn0501_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt "ps-13" "mb-13" cn0501_dma/irq
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@ -1,22 +0,0 @@
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####################################################################################
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## Copyright (c) 2018 - 2023 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := cn0501_coraz7s
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M_DEPS += ../common/cn0501_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_ad7768
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_pack/util_cpack2
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include ../../scripts/project-xilinx.mk
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@ -1,18 +0,0 @@
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###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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source ../common/cn0501_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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@ -1,30 +0,0 @@
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###############################################################################
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## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in ]; ## P12.10 IO8
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set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in ]; ## P12.9 IO9
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set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]]; ## P14.1 IO0
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set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]]; ## P14.2 IO1
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set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]]; ## P14.3 IO2
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set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]]; ## P14.4 IO3
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]]; ## P14.1 IO4
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]]; ## P14.2 IO5
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set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]]; ## P14.3 IO6
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set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]]; ## P14.4 IO7
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set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn ]; ## P12.8 IO10
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13
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set input_clock_period 31.25; # Period of input clock fMAX_DCLK=32MHz
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set hold_time 8.5;
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set setup_time 8.5;
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create_clock -name adc_clk -period $input_clock_period [get_ports clk_in]
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set_input_delay -clock adc_clk -max [expr $input_clock_period - $setup_time] [get_ports data_in[*]] -clock_fall -add_delay;
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set_input_delay -clock adc_clk -min $hold_time [get_ports data_in[*]] -clock_fall -add_delay;
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@ -1,19 +0,0 @@
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###############################################################################
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## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# load script
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project cn0501_coraz7s
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adi_project_files cn0501_coraz7s [list \
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"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" ]
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adi_project_run cn0501_coraz7s
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@ -1,149 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [ 1:0] btn,
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inout [ 5:0] led,
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input clk_in,
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input ready_in,
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input [ 7:0] data_in,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso
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);
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// internal signals
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wire [63:0] adc_gpio_i;
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wire [63:0] adc_gpio_o;
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wire [63:0] adc_gpio_t;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_buttons (
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.dio_t(gpio_t[1:0]),
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.dio_i(gpio_o[1:0]),
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.dio_o(gpio_i[1:0]),
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.dio_p(btn));
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ad_iobuf #(
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.DATA_WIDTH(6)
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) i_iobuf_leds (
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.dio_t(gpio_t[7:2]),
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.dio_i(gpio_o[7:2]),
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.dio_o(gpio_i[7:2]),
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.dio_p(led));
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assign gpio_i[63:8] = gpio_o[63:8];
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system_wrapper i_system_wrapper (
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.clk_in (clk_in),
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.ready_in (ready_in),
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.data_in (data_in),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o ());
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endmodule
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