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fmcomms2/a10soc: ip updates

main
Rejeesh Kutty 2016-05-04 13:41:25 -04:00
parent 92dcce1674
commit f4e5965936
1 changed files with 27 additions and 39 deletions
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66
projects/fmcomms2/common/fmcomms2_bd.qsys
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@ -9,19 +9,11 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element ad9361_clk_bridge
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element adc_pack
{
datum _sortIndex
{
value = "4";
value = "3";
type = "int";
}
datum sopceditor_expanded
@ -90,7 +82,7 @@
{
datum _sortIndex
{
value = "3";
value = "2";
type = "int";
}
datum sopceditor_expanded
@ -111,7 +103,7 @@
{
datum _sortIndex
{
value = "5";
value = "4";
type = "int";
}
datum sopceditor_expanded
@ -132,7 +124,7 @@
{
datum _sortIndex
{
value = "7";
value = "6";
type = "int";
}
datum sopceditor_expanded
@ -153,7 +145,7 @@
{
datum _sortIndex
{
value = "6";
value = "5";
type = "int";
}
datum sopceditor_expanded
@ -200,25 +192,31 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="axi_ad9361_device_clock"
internal="axi_ad9361.device_clock"
name="axi_ad9361_delay_clk"
internal="axi_ad9361.if_delay_clk"
type="clock"
dir="end" />
<interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
<interface
name="axi_ad9361_device_if"
internal="axi_ad9361.device_if"
type="conduit"
dir="end" />
<interface
name="axi_ad9361_l_clk"
internal="ad9361_clk_bridge.out_clk"
type="clock"
dir="start" />
<interface
name="axi_ad9361_s_axi"
internal="axi_ad9361.s_axi"
type="axi4lite"
dir="end" />
<interface
name="axi_ad9361_up_enable"
internal="axi_ad9361.if_up_enable"
type="conduit"
dir="end" />
<interface
name="axi_ad9361_up_txnrx"
internal="axi_ad9361.if_up_txnrx"
type="conduit"
dir="end" />
<interface
name="axi_dmac_adc_fifo_wr_clock"
internal="axi_dmac_adc.fifo_wr_clock" />
@ -259,20 +257,15 @@
dir="end" />
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
<module
name="ad9361_clk_bridge"
kind="altera_clock_bridge"
version="15.1"
enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
<parameter name="NUM_OF_CHANNELS" value="4" />
</module>
<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
<parameter name="ADC_DATAPATH_DISABLE" value="0" />
<parameter name="CMOS_OR_LVDS_N" value="0" />
<parameter name="DAC_DATAPATH_DISABLE" value="0" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="DEVICE_TYPE" value="0" />
<parameter name="ID" value="0" />
</module>
@ -331,6 +324,11 @@
version="15.1"
start="axi_ad9361.if_l_clk"
end="adc_pack.if_adc_clk" />
<connection
kind="clock"
version="15.1"
start="axi_ad9361.if_l_clk"
end="axi_ad9361.if_clk" />
<connection
kind="clock"
version="15.1"
@ -346,16 +344,6 @@
version="15.1"
start="axi_ad9361.if_l_clk"
end="axi_dmac_adc.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.1"
start="axi_ad9361.if_l_clk"
end="ad9361_clk_bridge.in_clk" />
<connection
kind="clock"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9361.delay_clock" />
<connection
kind="clock"
version="15.1"