Remove unused script
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## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
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## developed independently, and may be accompanied by separate and unique license
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## terms.
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##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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# adi_device_info_enc.tcl
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variable auto_set_param_list
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variable fpga_series_list
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variable fpga_family_list
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variable speed_grade_list
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variable dev_package_list
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variable xcvr_type_list
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# Parameter list for automatic assignament
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set auto_set_param_list {
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XCVR_TYPE \
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DEV_PACKAGE \
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SPEED_GRADE \
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FPGA_FAMILY \
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FPGA_TECHNOLOGY}
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# List for automatically assigned parameter values and encoded values
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# The list name must be the parameter name (lowercase), appending "_list" to it
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set fpga_technology_list { \
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{ 7series 0 } \
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{ ultrascale 1 } \
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{ ultrascale+ 2 }}
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set fpga_family_list { \
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{ artix 0 } \
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{ kintex 1 } \
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{ virtex 2 } \
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{ zynq 3 }}
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set speed_grade_list { \
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{ -1 10 } \
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{ -1L 11 } \
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{ -1H 12 } \
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{ -1HV 13 } \
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{ -1LV 14 } \
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{ -2 20 } \
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{ -2L 21 } \
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{ -2LV 22 } \
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{ -3 30 }}
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set dev_package_list { \
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{ rf 1 } \
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{ fl 2 } \
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{ ff 3 } \
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{ fb 4 } \
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{ hc 5 } \
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{ fh 6 } \
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{ cs 7 } \
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{ cp 8 } \
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{ ft 9 } \
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{ fg 10 } \
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{ sb 11 } \
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{ rb 12 } \
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{ rs 13 } \
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{ cl 14 } \
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{ sf 15 } \
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{ ba 16 } \
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{ fa 17 }}
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set xcvr_type_list { \
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{ GTPE2_NOT_SUPPORTED 1 } \
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{ GTXE2 2 } \
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{ GTHE2_NOT_SUPPORTED 3 } \
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{ GTZE2_NOT_SUPPORTED 4 } \
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{ GTHE3 5 } \
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{ GTYE3_NOT_SUPPORTED 6 } \
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{ GTRE4_NOT_SUPPORTED 7 } \
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{ GTHE4 8 } \
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{ GTYE4_NOT_SUPPORTED 9 } \
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{ GTME4_NOT_SUPPORTED 10}}
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## ***************************************************************************
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## ***************************************************************************
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