From f45408d6a97a82006447a4a947c703f324e4a84b Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 15 Apr 2019 08:59:06 +0100 Subject: [PATCH] util_adxcvr: Expose GTY4 parameters required for 15Gbps link These parameters must be overwritten when the link is at 15Gbps. The parameters have a GTY4_ prefix since the same parameters are shared between GTY4 and GTH4 having different default values. --- library/xilinx/util_adxcvr/util_adxcvr.v | 113 +++++++++++++++---- library/xilinx/util_adxcvr/util_adxcvr_xch.v | 13 ++- library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 7 +- 3 files changed, 107 insertions(+), 26 deletions(-) diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index 15356eca4..342443f6b 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -55,6 +55,7 @@ module util_adxcvr #( parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, + parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000, // cpll-configuration @@ -64,6 +65,10 @@ module util_adxcvr #( parameter [15:0] CPLL_CFG1 = 16'b0000000000100011, parameter [15:0] CPLL_CFG2 = 16'b0000000000000010, parameter [15:0] CPLL_CFG3 = 16'b0000000000000000, + parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000, + parameter integer GTY4_PREIQ_FREQ_BST = 0, + parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011, + parameter [15:0] GTY4_RXPI_CFG0 = 16'b0000000100000000, // tx-configuration @@ -1130,7 +1135,8 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), - .QPLL_CFG4 (QPLL_CFG4)) + .QPLL_CFG4 (QPLL_CFG4), + .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_0 ( .qpll_ref_clk (qpll_ref_clk_0), .qpll_sel (qpll_sel_0), @@ -1179,7 +1185,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 0) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 0) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_0 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1285,7 +1295,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 1) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 1) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_1 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1391,7 +1405,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 2) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 2) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_2 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1497,7 +1515,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 3) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 3) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_3 ( .qpll2ch_clk (qpll2ch_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0), @@ -1598,7 +1620,8 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), - .QPLL_CFG4 (QPLL_CFG4)) + .QPLL_CFG4 (QPLL_CFG4), + .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_4 ( .qpll_ref_clk (qpll_ref_clk_4), .qpll_sel (qpll_sel_4), @@ -1647,7 +1670,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 4) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 4) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_4 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1753,7 +1780,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 5) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 5) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_5 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1859,7 +1890,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 6) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 6) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_6 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -1965,7 +2000,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 7) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 7) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_7 ( .qpll2ch_clk (qpll2ch_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4), @@ -2066,7 +2105,8 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), - .QPLL_CFG4 (QPLL_CFG4)) + .QPLL_CFG4 (QPLL_CFG4), + .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_8 ( .qpll_ref_clk (qpll_ref_clk_8), .qpll_sel (qpll_sel_8), @@ -2115,7 +2155,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 8) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 8) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_8 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2221,7 +2265,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 9) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 9) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_9 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2327,7 +2375,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 10) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 10) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_10 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2433,7 +2485,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 11) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 11) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_11 ( .qpll2ch_clk (qpll2ch_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8), @@ -2534,7 +2590,8 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), - .QPLL_CFG4 (QPLL_CFG4)) + .QPLL_CFG4 (QPLL_CFG4), + .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_12 ( .qpll_ref_clk (qpll_ref_clk_12), .qpll_sel (qpll_sel_12), @@ -2583,7 +2640,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 12) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 12) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_12 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2689,7 +2750,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 13) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 13) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_13 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2795,7 +2860,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 14) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 14) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_14 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), @@ -2901,7 +2970,11 @@ module util_adxcvr #( .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), .RX_PMA_CFG (RX_PMA_CFG), .RX_CDR_CFG (RX_CDR_CFG), - .RX_POLARITY ((RX_LANE_INVERT >> 15) & 1)) + .RX_POLARITY ((RX_LANE_INVERT >> 15) & 1), + .GTY4_CH_HSPMUX (GTY4_CH_HSPMUX), + .GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), + .GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), + .GTY4_RXPI_CFG0 (GTY4_RXPI_CFG0)) i_xch_15 ( .qpll2ch_clk (qpll2ch_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index cd615ee97..c99d467b3 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -48,6 +48,11 @@ module util_adxcvr_xch #( parameter [15:0] CPLL_CFG2 = 16'b0000000000000010, parameter [15:0] CPLL_CFG3 = 16'b0000000000000000, + parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000, + parameter integer GTY4_PREIQ_FREQ_BST = 0, + parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011, + parameter [15:0] GTY4_RXPI_CFG0 = 16'b0000000100000000, + parameter integer TX_OUT_DIV = 1, parameter integer TX_CLK25_DIV = 20, parameter integer TX_POLARITY = 0, @@ -2459,7 +2464,7 @@ module util_adxcvr_xch #( .CHAN_BOND_SEQ_2_ENABLE (4'b1111), .CHAN_BOND_SEQ_2_USE ("FALSE"), .CHAN_BOND_SEQ_LEN (1), - .CH_HSPMUX (16'b0010000000100000), + .CH_HSPMUX (GTY4_CH_HSPMUX), .CKCAL1_CFG_0 (16'b1100000011000000), .CKCAL1_CFG_1 (16'b0001000011000000), .CKCAL1_CFG_2 (16'b0010000000001000), @@ -2588,11 +2593,11 @@ module util_adxcvr_xch #( .PD_TRANS_TIME_FROM_P2 (12'b000000111100), .PD_TRANS_TIME_NONE_P2 (8'b00011001), .PD_TRANS_TIME_TO_P2 (8'b01100100), - .PREIQ_FREQ_BST (0), + .PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST), .RATE_SW_USE_DRP (1'b1), .RCLK_SIPO_DLY_ENB (1'b0), .RCLK_SIPO_INV_EN (1'b0), - .RTX_BUF_CML_CTRL (3'b011), + .RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL), .RTX_BUF_TERM_CTRL (2'b00), .RXBUFRESET_TIME (5'b00011), .RXBUF_ADDR_MODE ("FAST"), @@ -2712,7 +2717,7 @@ module util_adxcvr_xch #( .RXPHSAMP_CFG (16'b0010000100000000), .RXPHSLIP_CFG (16'b1001100100110011), .RXPH_MONITOR_SEL (5'b00000), - .RXPI_CFG0 (16'b0000000100000000), + .RXPI_CFG0 (GTY4_RXPI_CFG0), .RXPI_CFG1 (16'b0000000001010100), .RXPMACLK_SEL ("DATA"), .RXPMARESET_TIME (5'b00011), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index c04844af7..a4fe5cd5d 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -50,7 +50,10 @@ module util_adxcvr_xcm #( parameter [15:0] QPLL_CFG2 = 16'b0000111111000000, parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, - parameter [15:0] QPLL_CFG4 = 16'b0000000000000011) ( + parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, + + parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000 +) ( // reset and clocks @@ -549,7 +552,7 @@ module util_adxcvr_xcm #( .COMMON_CFG0 (16'b0000000000000000), .COMMON_CFG1 (16'b0000000000000000), .POR_CFG (16'b0000000000000000), - .PPF0_CFG (16'b0000100000000000), + .PPF0_CFG (GTY4_PPF0_CFG), .PPF1_CFG (16'b0000011000000000), .QPLL0CLKOUT_RATE ("HALF"), .QPLL0_CFG0 (QPLL_CFG0),