diff --git a/library/common/altera/ad_jesd_align.v b/library/common/altera/ad_jesd_align.v index 6ebb12a3e..17b171a4e 100644 --- a/library/common/altera/ad_jesd_align.v +++ b/library/common/altera/ad_jesd_align.v @@ -58,29 +58,39 @@ module ad_jesd_align ( // internal registers + reg [ 3:0] rx_sof_hold = 'd0; reg [31:0] rx_ip_data_d = 'd0; reg [31:0] rx_data = 'd0; + // internal signals + + wire [ 3:0] rx_sof_s; + // dword may contain more than one frame per clock + assign rx_sof_s = (rx_sof == 4'd0) ? rx_sof_hold : rx_sof; + always @(posedge rx_clk) begin + if (rx_sof != 4'd0) begin + rx_sof_hold <= rx_sof; + end rx_ip_data_d <= rx_ip_data; - if (rx_sof[3] == 1'b1) begin + if (rx_sof_s[3] == 1'b1) begin rx_data[31:24] <= rx_ip_data[ 7: 0]; rx_data[23:16] <= rx_ip_data[15: 8]; rx_data[15: 8] <= rx_ip_data[23:16]; rx_data[ 7: 0] <= rx_ip_data[31:24]; - end else if (rx_sof[2] == 1'b1) begin + end else if (rx_sof_s[2] == 1'b1) begin rx_data[31:24] <= rx_ip_data[31:24]; rx_data[23:16] <= rx_ip_data_d[ 7: 0]; rx_data[15: 8] <= rx_ip_data_d[15: 8]; rx_data[ 7: 0] <= rx_ip_data_d[23:16]; - end else if (rx_sof[1] == 1'b1) begin + end else if (rx_sof_s[1] == 1'b1) begin rx_data[31:24] <= rx_ip_data[23:16]; rx_data[23:16] <= rx_ip_data[31:24]; rx_data[15: 8] <= rx_ip_data_d[ 7: 0]; rx_data[ 7: 0] <= rx_ip_data_d[15: 8]; - end else if (rx_sof[0] == 1'b1) begin + end else if (rx_sof_s[0] == 1'b1) begin rx_data[31:24] <= rx_ip_data[15: 8]; rx_data[23:16] <= rx_ip_data[23:16]; rx_data[15: 8] <= rx_ip_data[31:24]; diff --git a/projects/ad9671_fmc/a5gt/system_bd.qsys b/projects/ad9671_fmc/a5gt/system_bd.qsys index 75a7b82e9..dfc1eece2 100644 --- a/projects/ad9671_fmc/a5gt/system_bd.qsys +++ b/projects/ad9671_fmc/a5gt/system_bd.qsys @@ -115,6 +115,14 @@ type = "String"; } } + element sys_ddr3_dmaconnect.s0 + { + datum baseAddress + { + value = "0"; + type = "String"; + } + } element sys_ddr3_interconnect.s0 { datum _lockedAddress @@ -128,14 +136,6 @@ type = "String"; } } - element sys_ddr3_dmaconnect.s0 - { - datum baseAddress - { - value = "0"; - type = "String"; - } - } element sys_jesd204b_s1_connect.s0 { datum baseAddress @@ -152,14 +152,6 @@ type = "String"; } } - element sys_timer.s1 - { - datum baseAddress - { - value = "86025376"; - type = "String"; - } - } element sys_ethernet_desc_mem.s1 { datum baseAddress @@ -168,6 +160,14 @@ type = "String"; } } + element sys_timer.s1 + { + datum baseAddress + { + value = "86025376"; + type = "String"; + } + } element sys_int_mem.s1 { datum _lockedAddress @@ -189,6 +189,14 @@ type = "String"; } } + element sys_tcm_mem.s2 + { + datum baseAddress + { + value = "86016000"; + type = "String"; + } + } element sys_int_mem.s2 { datum _lockedAddress @@ -202,14 +210,6 @@ type = "String"; } } - element sys_tcm_mem.s2 - { - datum baseAddress - { - value = "86016000"; - type = "String"; - } - } element axi_ad9671.s_axi { datum baseAddress @@ -1596,18 +1596,18 @@ - + - + - + @@ -1640,7 +1640,7 @@ version="13.1" enabled="1" name="sys_jesd204b_s1_rx_clk"> - + @@ -1668,7 +1668,7 @@ - + @@ -1910,7 +1910,7 @@ - + @@ -1944,7 +1944,7 @@ - + diff --git a/projects/ad9671_fmc/a5gt/system_project.tcl b/projects/ad9671_fmc/a5gt/system_project.tcl index d7e12ad72..bf88d7910 100644 --- a/projects/ad9671_fmc/a5gt/system_project.tcl +++ b/projects/ad9671_fmc/a5gt/system_project.tcl @@ -28,20 +28,12 @@ set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk set_location_assignment PIN_R1 -to rx_data[0] set_location_assignment PIN_R2 -to "rx_data[0](n)" -set_location_assignment PIN_AE1 -to rx_data[1] -set_location_assignment PIN_AE2 -to "rx_data[1](n)" -set_location_assignment PIN_U1 -to rx_data[2] -set_location_assignment PIN_U2 -to "rx_data[2](n)" -set_location_assignment PIN_AA1 -to rx_data[3] -set_location_assignment PIN_AA2 -to "rx_data[3](n)" +set_location_assignment PIN_U1 -to rx_data[1] +set_location_assignment PIN_U2 -to "rx_data[1](n)" set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0] set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2] -set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3] set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0] set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1] -set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2] -set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3] # jesd signals diff --git a/projects/ad9671_fmc/a5gt/system_top.v b/projects/ad9671_fmc/a5gt/system_top.v index 8c1614a66..6ca90ebfe 100644 --- a/projects/ad9671_fmc/a5gt/system_top.v +++ b/projects/ad9671_fmc/a5gt/system_top.v @@ -161,7 +161,7 @@ module system_top ( // lane interface input ref_clk; - input [ 3:0] rx_data; + input [ 1:0] rx_data; output rx_sync; output rx_sysref; @@ -223,18 +223,18 @@ module system_top ( wire adc_mon_valid_s; wire [127:0] adc_mon_data_s; wire [ 3:0] rx_ip_sof_s; - wire [127:0] rx_ip_data_s; - wire [127:0] rx_data_s; + wire [ 63:0] rx_ip_data_s; + wire [ 63:0] rx_data_s; wire rx_sw_rstn_s; wire rx_sysref_s; wire rx_err_s; wire rx_ready_s; wire [ 3:0] rx_rst_state_s; wire rx_lane_aligned_s; - wire [ 3:0] rx_analog_reset_s; - wire [ 3:0] rx_digital_reset_s; - wire [ 3:0] rx_cdr_locked_s; - wire [ 3:0] rx_cal_busy_s; + wire [ 1:0] rx_analog_reset_s; + wire [ 1:0] rx_digital_reset_s; + wire [ 1:0] rx_cdr_locked_s; + wire [ 1:0] rx_cal_busy_s; wire rx_pll_locked_s; wire [ 15:0] rx_xcvr_status_s; @@ -290,7 +290,7 @@ module system_top ( genvar n; generate - for (n = 0; n < 4; n = n + 1) begin: g_align_1 + for (n = 0; n < 2; n = n + 1) begin: g_align_1 ad_jesd_align i_jesd_align ( .rx_clk (rx_clk), .rx_sof (rx_ip_sof_s), @@ -299,15 +299,15 @@ module system_top ( end endgenerate - assign rx_xcvr_status_s[15:15] = 1'd0; - assign rx_xcvr_status_s[14:14] = rx_sync; - assign rx_xcvr_status_s[13:13] = rx_ready_s; - assign rx_xcvr_status_s[12:12] = rx_pll_locked_s; - assign rx_xcvr_status_s[11: 8] = rx_rst_state_s; - assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s; - assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s; + assign rx_xcvr_status_s[15:11] = 5'd0; + assign rx_xcvr_status_s[10:10] = rx_sync; + assign rx_xcvr_status_s[ 9: 9] = rx_ready_s; + assign rx_xcvr_status_s[ 8: 8] = rx_pll_locked_s; + assign rx_xcvr_status_s[ 7: 4] = rx_rst_state_s; + assign rx_xcvr_status_s[ 3: 2] = rx_cdr_locked_s; + assign rx_xcvr_status_s[ 1: 0] = rx_cal_busy_s; - ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst ( + ad_xcvr_rx_rst #(.NUM_OF_LANES (2)) i_xcvr_rx_rst ( .rx_clk (rx_clk), .rx_rstn (sys_resetn), .rx_sw_rstn (rx_sw_rstn_s), diff --git a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl index cdb351c9e..1fe373b01 100755 --- a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl +++ b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl @@ -14,27 +14,27 @@ set spi_sdi_i [create_bd_port -dir I spi_sdi_i] set rx_ref_clk [create_bd_port -dir I rx_ref_clk] set rx_sync [create_bd_port -dir O rx_sync] set rx_sysref [create_bd_port -dir O rx_sysref] -set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] -set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] +set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p] +set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n] # adc peripherals set axi_ad9671_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core] -set_property -dict [list CONFIG.PCORE_4L_2L_N {1}] [get_bd_cells axi_ad9671_core] +set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core] set axi_ad9671_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9671_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9671_jesd -set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9671_jesd +set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9671_jesd set axi_ad9671_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9671_gt] -set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] [get_bd_cells axi_ad9671_gt] +set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {2}] [get_bd_cells axi_ad9671_gt] set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_ad9671_gt -set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {2}] $axi_ad9671_gt -set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {2}] $axi_ad9671_gt +set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9671_gt +set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9671_gt set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_ad9671_gt set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_ad9671_gt set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9671_gt -set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff40200020}] $axi_ad9671_gt +set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9671_gt set axi_ad9671_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9671_dma] set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9671_dma @@ -180,9 +180,9 @@ connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma/m_dest_axi_ar set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {170}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon connect_bd_net -net axi_ad9671_gt_rx_mon_data [get_bd_pins axi_ad9671_gt/rx_mon_data] diff --git a/projects/ad9671_fmc/zc706/system_constr.xdc b/projects/ad9671_fmc/zc706/system_constr.xdc index 6f6a0215b..8e664a266 100755 --- a/projects/ad9671_fmc/zc706/system_constr.xdc +++ b/projects/ad9671_fmc/zc706/system_constr.xdc @@ -6,12 +6,8 @@ set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P diff --git a/projects/ad9671_fmc/zc706/system_top.v b/projects/ad9671_fmc/zc706/system_top.v index d795d1a00..6ef80b897 100755 --- a/projects/ad9671_fmc/zc706/system_top.v +++ b/projects/ad9671_fmc/zc706/system_top.v @@ -148,8 +148,8 @@ module system_top ( output rx_sysref_n; output rx_sync_p; output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; + input [ 1:0] rx_data_p; + input [ 1:0] rx_data_n; output spi_ad9671_csn; output spi_ad9671_clk;