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zcu102- updates

main
Rejeesh Kutty 2016-05-10 15:40:32 -04:00
parent 16e3a0e569
commit f3f5353944
2 changed files with 375 additions and 222 deletions
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519
projects/common/zcu102/zcu102_system_bd.tcl
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@ -2,45 +2,18 @@
# create board design
# default ports
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
create_bd_port -dir O spi0_csn_2_o
create_bd_port -dir O spi0_csn_1_o
create_bd_port -dir O spi0_csn_0_o
create_bd_port -dir I spi0_csn_i
create_bd_port -dir I spi0_clk_i
create_bd_port -dir O spi0_clk_o
create_bd_port -dir I spi0_sdo_i
create_bd_port -dir O spi0_sdo_o
create_bd_port -dir I spi0_sdi_i
create_bd_port -dir O -from 2 -to 0 spi1_csn
create_bd_port -dir O spi1_sclk
create_bd_port -dir O spi1_mosi
create_bd_port -dir I spi1_miso
create_bd_port -dir O spi1_csn_2_o
create_bd_port -dir O spi1_csn_1_o
create_bd_port -dir O spi1_csn_0_o
create_bd_port -dir I spi1_csn_i
create_bd_port -dir I spi1_clk_i
create_bd_port -dir O spi1_clk_o
create_bd_port -dir I spi1_sdo_i
create_bd_port -dir O spi1_sdo_o
create_bd_port -dir I spi1_sdi_i
create_bd_port -dir I -from 63 -to 0 gpio_i
create_bd_port -dir O -from 63 -to 0 gpio_o
create_bd_port -dir O -from 63 -to 0 gpio_t
# hdmi interface
create_bd_port -dir O hdmi_out_clk
create_bd_port -dir O hdmi_hsync
create_bd_port -dir O hdmi_vsync
create_bd_port -dir O hdmi_data_e
create_bd_port -dir O -from 23 -to 0 hdmi_data
# spdif audio
create_bd_port -dir O spdif
create_bd_port -dir I -from 95 -to 0 gpio_i
create_bd_port -dir O -from 95 -to 0 gpio_o
# interrupts
@ -58,157 +31,373 @@ create_bd_port -dir I -type intr ps_intr_10
create_bd_port -dir I -type intr ps_intr_11
create_bd_port -dir I -type intr ps_intr_12
create_bd_port -dir I -type intr ps_intr_13
create_bd_port -dir I -type intr ps_intr_14
create_bd_port -dir I -type intr ps_intr_15
# instance: sys_ps7
# instance: sys_ps8
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
set_property -dict [list CONFIG.preset {ZC706}] $sys_ps7
set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
set sys_ps8 [create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:1.0 sys_ps8]
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
# defaults -- remove after board is supported in the tool
set_property -dict [list\
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
CONFIG.PSU__SD1__GRP_POW__IO {MIO 43} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
CONFIG.PSU__SD1__GRP_WP__IO {MIO 44} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__SLOT_TYPE {SD} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
CONFIG.PSU__USE__M_AXI_GP2 {1} \
CONFIG.PSU__MAXIGP2__DATA_WIDTH {64} \
CONFIG.PSU__GT__LANE0_REF_SEL {Ref Clk0} \
CONFIG.PSU__GT__LANE1_REF_SEL {Ref Clk0} \
CONFIG.PSU__GT__LANE2_REF_SEL {Ref Clk2} \
CONFIG.PSU__GT__LANE3_REF_SEL {Ref Clk1} \
CONFIG.PSU__GT__REF_SEL0 {100} \
CONFIG.PSU__GT__REF_SEL1 {100} \
CONFIG.PSU__GT__REF_SEL2 {26} \
CONFIG.PSU__GT__REF_SEL3 {125} \
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_IO {MIO 31} \
CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {Root Port} \
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \
CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \
CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {1} \
CONFIG.PSU__PCIE__LANE0__ENABLE {1} \
CONFIG.PSU__PCIE__LANE0__IO {GT Lane0} \
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
CONFIG.PSU__PCIE__MAXIMUM_LINK_WIDTH {x1} \
CONFIG.PSU__PCIE__LINK_SPEED {5.0 Gb/s} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SATA__LANE1__ENABLE {1} \
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
CONFIG.PSU__DDRC__VREF {1} \
CONFIG.PSU__DDRC__ECC {0} \
CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
CONFIG.PSU__DDRC__DRAM_WIDTH {8 Bits} \
CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
CONFIG.PSU__DDRC__FREQ_MHZ {1066.50} \
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {2} \
CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
CONFIG.PSU__DDRC__CL {15} \
CONFIG.PSU__DDRC__T_RCD {15} \
CONFIG.PSU__DDRC__T_RP {15} \
CONFIG.PSU__DDRC__CWL {14} \
CONFIG.PSU__DDRC__AL {0} \
CONFIG.PSU__DDRC__BL {8} \
CONFIG.PSU__DDRC__T_RC {46.5} \
CONFIG.PSU__DDRC__T_RAS_MIN {33} \
CONFIG.PSU__DDRC__T_FAW {21.0} \
CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {0} \
CONFIG.PSU__DDRC__RD_DBI_ENABLE {0} \
CONFIG.PSU__DDRC__WR_DBI_ENABLE {0} \
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
CONFIG.PSU__DDRC__DATA_MASK {1} \
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
CONFIG.PSU__DDRC__BRC_MAPPING {0} \
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
CONFIG.PSU__DDRC__FGRM {0} \
CONFIG.PSU__DDRC__LP_ASR {0} \
CONFIG.PSU__DDRC__UDIMM_INDICATOR {1} \
CONFIG.PSU__DDRC__RDIMM_INDICATOR {0} \
CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {66} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {57} \
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.508} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {72} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__DBG_TRACE__ENABLE {1} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_FPD__ENABLE {1} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_TSTMP__ENABLE {1} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {39} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {17} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DPDMA__ENABLE {1} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GDMA__ENABLE {1} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN__ENABLE {1} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS__ENABLE {1} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRL_APB__IOU_SWITCH__ENABLE {1} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__ADMA__ENABLE {1} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__DBG_LPD__ENABLE {1} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__PCAP__ENABLE {1} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__LPD_LSBUS__ENABLE {1} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__LPD_SWITCH__ENABLE {1} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__TIMESTAMP__ENABLE {1} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
] $sys_ps8
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
set_property CONFIG.PSU__USE__M_AXI_GP2 {1} $sys_ps8
set_property CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} $sys_ps8
set_property CONFIG.PSU__FPGA_PL0_ENABLE {1} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} $sys_ps8
set_property CONFIG.PSU__FPGA_PL1_ENABLE {1} $sys_ps8
set_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} $sys_ps8
set_property CONFIG.PSU__USE__IRQ0 {1} $sys_ps8
set_property CONFIG.PSU__USE__IRQ1 {1} $sys_ps8
set_property CONFIG.PSU__GPIO0_EMIO__PERIPHERAL__ENABLE {1} $sys_ps8
set_property -dict [list\
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO} \
] $sys_ps8
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
# hdmi peripherals
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
# audio peripherals
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 sys_audio_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
ad_connect sys_cpu_clk sys_ps8/pl_clk0
ad_connect sys_200m_clk sys_ps8/pl_clk1
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
ad_connect sys_rstgen/ext_reset_in GND
# interface connections
# gpio
ad_connect ddr sys_ps7/DDR
ad_connect gpio_i sys_ps7/GPIO_I
ad_connect gpio_o sys_ps7/GPIO_O
ad_connect gpio_t sys_ps7/GPIO_T
ad_connect fixed_io sys_ps7/FIXED_IO
ad_connect iic_main axi_iic_main/iic
ad_connect sys_200m_clk axi_hdmi_clkgen/clk
ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
# spi connections
# spi
ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
ad_connect sys_ps8/emio_spi0_sclk_i sys_ps8/emio_spi0_sclk_o
ad_connect sys_ps8/emio_spi0_m_i sys_ps8/emio_spi0_m_o
ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
ad_connect spi0_csn sys_ps8/emio_spi0_ss_o_n
ad_connect spi0_sclk sys_ps8/emio_spi0_sclk_o
ad_connect spi0_mosi sys_ps8/emio_spi0_m_o
ad_connect spi0_miso sys_ps8/emio_spi0_s_i
# hdmi
ad_connect sys_ps8/emio_spi1_ss_i_n VCC
ad_connect sys_ps8/emio_spi1_sclk_i sys_ps8/emio_spi1_sclk_o
ad_connect sys_ps8/emio_spi1_m_i sys_ps8/emio_spi1_m_o
ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
ad_connect axi_hdmi_core/hdmi_24_hsync hdmi_hsync
ad_connect axi_hdmi_core/hdmi_24_vsync hdmi_vsync
ad_connect axi_hdmi_core/hdmi_24_data_e hdmi_data_e
ad_connect axi_hdmi_core/hdmi_24_data hdmi_data
ad_connect axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
ad_connect axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
ad_connect axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
ad_connect axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
ad_connect axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
# spdif audio
ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
ad_connect spdif axi_spdif_tx_core/spdif_tx_o
ad_connect spi1_csn sys_ps8/emio_spi1_ss_o_n
ad_connect spi1_sclk sys_ps8/emio_spi1_sclk_o
ad_connect spi1_mosi sys_ps8/emio_spi1_m_o
ad_connect spi1_miso sys_ps8/emio_spi1_s_i
# interrupts
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
ad_connect sys_concat_intc/In13 ps_intr_13
ad_connect sys_concat_intc/In12 ps_intr_12
ad_connect sys_concat_intc/In11 ps_intr_11
ad_connect sys_concat_intc/In10 ps_intr_10
ad_connect sys_concat_intc/In9 ps_intr_09
ad_connect sys_concat_intc/In8 ps_intr_08
ad_connect sys_concat_intc/In7 ps_intr_07
ad_connect sys_concat_intc/In6 ps_intr_06
ad_connect sys_concat_intc/In5 ps_intr_05
ad_connect sys_concat_intc/In4 ps_intr_04
ad_connect sys_concat_intc/In3 ps_intr_03
ad_connect sys_concat_intc/In2 ps_intr_02
ad_connect sys_concat_intc/In1 ps_intr_01
ad_connect sys_concat_intc/In0 ps_intr_00
set sys_concat_intc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_0]
set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_0
# interconnects
set sys_concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc_1]
set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc_1
ad_cpu_interconnect 0x41600000 axi_iic_main
ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
ad_cpu_interconnect 0x43000000 axi_hdmi_dma
ad_cpu_interconnect 0x70e00000 axi_hdmi_core
ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
ad_connect sys_concat_intc_1/In7 ps_intr_15
ad_connect sys_concat_intc_1/In6 ps_intr_14
ad_connect sys_concat_intc_1/In5 ps_intr_13
ad_connect sys_concat_intc_1/In4 ps_intr_12
ad_connect sys_concat_intc_1/In3 ps_intr_11
ad_connect sys_concat_intc_1/In2 ps_intr_10
ad_connect sys_concat_intc_1/In1 ps_intr_09
ad_connect sys_concat_intc_1/In0 ps_intr_08
ad_connect sys_concat_intc_0/In7 ps_intr_07
ad_connect sys_concat_intc_0/In6 ps_intr_06
ad_connect sys_concat_intc_0/In5 ps_intr_05
ad_connect sys_concat_intc_0/In4 ps_intr_04
ad_connect sys_concat_intc_0/In3 ps_intr_03
ad_connect sys_concat_intc_0/In2 ps_intr_02
ad_connect sys_concat_intc_0/In1 ps_intr_01
ad_connect sys_concat_intc_0/In0 ps_intr_00

78
projects/common/zcu102/zcu102_system_constr.xdc
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@ -1,63 +1,27 @@
# constraints
# hdmi
set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_vsync]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_hsync]
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data_e]
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[0]]
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[1]]
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[2]]
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[3]]
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[4]]
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[5]]
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[6]]
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[7]]
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[8]]
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[9]]
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[10]]
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[11]]
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[12]]
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[13]]
set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[14]]
set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[15]]
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[16]]
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[17]]
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[18]]
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[19]]
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[20]]
set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[21]]
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[22]]
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_data[23]]
# spdif
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports spdif]
# iic
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda]
# gpio (switches, leds and such)
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3
set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER
set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[0]] ; ## GPIO_DIP_SW0
set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[1]] ; ## GPIO_DIP_SW1
set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[2]] ; ## GPIO_DIP_SW2
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[3]] ; ## GPIO_DIP_SW3
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[4]] ; ## GPIO_DIP_SW4
set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[5]] ; ## GPIO_DIP_SW5
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[6]] ; ## GPIO_DIP_SW6
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[7]] ; ## GPIO_DIP_SW7
set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[8]] ; ## GPIO_SW_E
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[9]] ; ## GPIO_SW_S
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[10]] ; ## GPIO_SW_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[11]] ; ## GPIO_SW_W
set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_i[12]] ; ## GPIO_SW_C
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[0]] ; ## GPIO_LED_0
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[1]] ; ## GPIO_LED_1
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[2]] ; ## GPIO_LED_2
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[3]] ; ## GPIO_LED_3
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[4]] ; ## GPIO_LED_4
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[5]] ; ## GPIO_LED_5
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[6]] ; ## GPIO_LED_6
set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS25} [get_ports gpio_bd_o[7]] ; ## GPIO_LED_7