From f3f46867597008925585cb710b4f1dbdbb62c15c Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Fri, 26 Aug 2022 11:41:39 +0300 Subject: [PATCH] axi_ltc2387: Update up_adc_common and up_adc_channel instances * Cosmetic changes also Signed-off-by: Iulia Moldovan --- library/axi_ltc2387/axi_ltc2387.v | 95 ++++++++++++----------- library/axi_ltc2387/axi_ltc2387_channel.v | 92 +++++++++++----------- library/axi_ltc2387/axi_ltc2387_if.v | 69 ++++++++-------- library/axi_ltc2387/axi_ltc2387_ip.tcl | 2 - 4 files changed, 129 insertions(+), 129 deletions(-) diff --git a/library/axi_ltc2387/axi_ltc2387.v b/library/axi_ltc2387/axi_ltc2387.v index f577fc443..0dc8e6fd7 100644 --- a/library/axi_ltc2387/axi_ltc2387.v +++ b/library/axi_ltc2387/axi_ltc2387.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -56,70 +56,70 @@ module axi_ltc2387 #( // adc interface - input ref_clk, - input clk_gate, - input dco_p, - input dco_n, - input da_p, - input da_n, - input db_p, - input db_n, + input ref_clk, + input clk_gate, + input dco_p, + input dco_n, + input da_p, + input da_n, + input db_p, + input db_n, // dma interface - output adc_valid, - output [OUT_RES-1:0] adc_data, - input adc_dovf, + output adc_valid, + output [OUT_RES-1:0] adc_data, + input adc_dovf, // axi interface - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [15:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [15:0] s_axi_araddr, - output s_axi_arready, - output s_axi_rvalid, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - input s_axi_rready, - input [ 2:0] s_axi_awprot, - input [ 2:0] s_axi_arprot + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot ); // internal signals - wire [15:0] adc_data_s; + wire [15:0] adc_data_s; wire adc_or_s; - wire [ 1:0] up_dld_s; - wire [ 9:0] up_dwdata_s; - wire [ 9:0] up_drdata_s; + wire [ 1:0] up_dld_s; + wire [ 9:0] up_dwdata_s; + wire [ 9:0] up_drdata_s; wire delay_locked_s; wire up_status_pn_err_s; wire up_status_pn_oos_s; wire up_status_or_s; wire up_rreq_s; - wire [13:0] up_raddr_s; - wire [31:0] up_rdata_s[0:2]; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:2]; wire up_rack_s[0:2]; wire up_wack_s[0:2]; wire up_wreq_s; - wire [13:0] up_waddr_s; - wire [31:0] up_wdata_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; // internal registers reg up_wack = 'd0; - reg [31:0] up_rdata = 'd0; + reg [31:0] up_rdata = 'd0; reg up_rack = 'd0; // internal signals @@ -130,8 +130,8 @@ module axi_ltc2387 #( wire up_clk; wire up_rstn; wire delay_rst; - wire [ADC_RES-1:0] adc_data_ch_s; wire adc_valid_ch_s; + wire [ADC_RES-1:0] adc_data_ch_s; // signal name changes @@ -160,7 +160,7 @@ module axi_ltc2387 #( .IO_DELAY_GROUP (IO_DELAY_GROUP), .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), .RESOLUTION (ADC_RES), - .IODELAY_CTRL(IODELAY_CTRL), + .IODELAY_CTRL (IODELAY_CTRL), .TWOLANES (TWOLANES) ) i_if ( .clk (ref_clk), @@ -215,8 +215,8 @@ module axi_ltc2387 #( up_delay_cntrl #( .INIT_DELAY (ADC_INIT_DELAY), - .DATA_WIDTH(2), - .BASE_ADDRESS(6'h02) + .DATA_WIDTH (2), + .BASE_ADDRESS (6'h02) ) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), @@ -248,7 +248,7 @@ module axi_ltc2387 #( .DRP_DISABLE (6'h00), .USERPORTS_DISABLE (USERPORTS_DISABLE), .GPIO_DISABLE (0), - .START_CODE_DISABLE(0) + .START_CODE_DISABLE (0) ) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), @@ -268,6 +268,7 @@ module axi_ltc2387 #( .adc_ext_sync_manual_req(), .adc_num_lanes (), .adc_custom_control(), + .adc_crc_enable (), .adc_sdr_ddr_n (), .adc_symb_op (), .adc_symb_8_16b (), diff --git a/library/axi_ltc2387/axi_ltc2387_channel.v b/library/axi_ltc2387/axi_ltc2387_channel.v index a3a9f6bfa..bc0d3629d 100644 --- a/library/axi_ltc2387/axi_ltc2387_channel.v +++ b/library/axi_ltc2387/axi_ltc2387_channel.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -37,69 +37,67 @@ module axi_ltc2387_channel #( - // parameters - - parameter ADC_RES = 16, - parameter OUT_RES = 16, - parameter TWOLANES = 1, - parameter USERPORTS_DISABLE = 0, - parameter DATAFORMAT_DISABLE = 0 + parameter ADC_RES = 16, + parameter OUT_RES = 16, + parameter TWOLANES = 1, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0 ) ( // adc interface - input adc_clk, - input adc_rst, - input adc_valid_in, - input [ADC_RES-1:0] adc_data_in, + input adc_clk, + input adc_rst, + input adc_valid_in, + input [ADC_RES-1:0] adc_data_in, // dma interface - output adc_enable, - output adc_valid, - output [OUT_RES-1:0] adc_data, + output adc_enable, + output adc_valid, + output [OUT_RES-1:0] adc_data, // error monitoring - output up_adc_pn_err, - output up_adc_pn_oos, - output up_adc_or, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, // processor interface - input up_rstn, - input up_clk, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output up_wack, - input up_rreq, - input [13:0] up_raddr, - output [31:0] up_rdata, - output up_rack + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack ); // internal signals - wire adc_dfmt_valid_s; - wire [15:0] adc_dfmt_data_s; - wire adc_dcfilter_valid_s; - wire adc_iqcor_enb_s; - wire adc_dcfilt_enb_s; - wire adc_dfmt_se_s; - wire adc_dfmt_type_s; - wire adc_dfmt_enable_s; - wire [15:0] adc_dcfilt_offset_s; - wire [15:0] adc_dcfilt_coeff_s; - wire [15:0] adc_iqcor_coeff_1_s; - wire [15:0] adc_iqcor_coeff_2_s; - wire [ 3:0] adc_pnseq_sel_s; - wire [ 3:0] adc_data_sel_s; - reg adc_pn_err; - wire adc_pn_err_s; + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + reg adc_pn_err; + wire adc_pn_err_s; - wire [15:0] expected_pattern; - wire [ADC_RES-1:0] test_pattern; + wire [ADC_RES-1:0] test_pattern; + wire [15:0] expected_pattern; assign adc_pn_err_s = adc_pn_err; @@ -178,6 +176,8 @@ module axi_ltc2387_channel #( .adc_pn_err (adc_pn_err_s), .adc_pn_oos (1'b0), .adc_or (1'b0), + .adc_status_header (8'd0), + .adc_crc_err (1'b0), .up_adc_pn_err (up_adc_pn_err), .up_adc_pn_oos (up_adc_pn_oos), .up_adc_or (up_adc_or), diff --git a/library/axi_ltc2387/axi_ltc2387_if.v b/library/axi_ltc2387/axi_ltc2387_if.v index 7957503bd..c9afb3d33 100644 --- a/library/axi_ltc2387/axi_ltc2387_if.v +++ b/library/axi_ltc2387/axi_ltc2387_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -49,50 +49,50 @@ module axi_ltc2387_if #( // delay interface - input up_clk, - input [ 1:0] up_dld, - input [ 9:0] up_dwdata, - output [ 9:0] up_drdata, - input delay_clk, - input delay_rst, - output delay_locked, + input up_clk, + input [ 1:0] up_dld, + input [ 9:0] up_dwdata, + output [ 9:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked, // adc interface - input clk, - input clk_gate, - input dco_p, - input dco_n, - input da_p, - input da_n, - input db_p, - input db_n, + input clk, + input clk_gate, + input dco_p, + input dco_n, + input da_p, + input da_n, + input db_p, + input db_n, - output adc_valid, + output adc_valid, output reg [RESOLUTION-1:0] adc_data ); - localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8; - localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4; - localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH; + localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8; + localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4; + localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH; // internal wires - wire da_p_int_s; - wire da_n_int_s; - wire db_p_int_s; - wire db_n_int_s; - wire dco; - wire dco_s; - wire [17:0] adc_data_int; + wire da_p_int_s; + wire da_n_int_s; + wire db_p_int_s; + wire db_n_int_s; + wire dco; + wire dco_s; + wire [17:0] adc_data_int; // internal registers - reg [WIDTH:0] adc_data_da_p = 'b0; - reg [WIDTH:0] adc_data_da_n = 'b0; - reg [WIDTH:0] adc_data_db_p = 'b0; - reg [WIDTH:0] adc_data_db_n = 'b0; - reg [2:0] clk_gate_d = 'b0; + reg [WIDTH:0] adc_data_da_p = 'b0; + reg [WIDTH:0] adc_data_da_n = 'b0; + reg [WIDTH:0] adc_data_db_p = 'b0; + reg [WIDTH:0] adc_data_db_n = 'b0; + reg [2:0] clk_gate_d = 'b0; // assignments @@ -118,6 +118,7 @@ module axi_ltc2387_if #( end // bits rearrangement + if (!TWOLANES) begin assign adc_data_int[17] = adc_data_da_p[7]; assign adc_data_int[16] = adc_data_da_n[7]; @@ -181,7 +182,7 @@ module axi_ltc2387_if #( ad_data_in #( .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), - .IDDR_CLK_EDGE("OPPOSITE_EDGE"), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE"), .IODELAY_CTRL (IODELAY_CTRL), .IODELAY_GROUP (IO_DELAY_GROUP), .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) @@ -201,7 +202,7 @@ module axi_ltc2387_if #( ad_data_in #( .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), - .IDDR_CLK_EDGE("OPPOSITE_EDGE"), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE"), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP), .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) diff --git a/library/axi_ltc2387/axi_ltc2387_ip.tcl b/library/axi_ltc2387/axi_ltc2387_ip.tcl index 3ef058cc0..893477ef3 100644 --- a/library/axi_ltc2387/axi_ltc2387_ip.tcl +++ b/library/axi_ltc2387/axi_ltc2387_ip.tcl @@ -1,5 +1,3 @@ -# ip - source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl