axi_dmac: Reset the fifo_rd_data if the DMA is off
Reset the fifo_rd_data if the DMA does not have an active transfer. Becasue all the DAC device cores are transfering the data from the FIFO interface to the data interface without any validation signal, DMA needs to put the data bus into a known state, to prevent the device core to send the last known data again and again.main
parent
d690a614c1
commit
f3daf0dacb
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@ -54,11 +54,11 @@ module dmac_dest_fifo_inf #(
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input response_eot,
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input en,
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output [DATA_WIDTH-1:0] dout,
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output valid,
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output underflow,
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output reg [DATA_WIDTH-1:0] dout,
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output reg valid,
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output reg underflow,
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output xfer_req,
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output reg xfer_req,
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output fifo_ready,
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input fifo_valid,
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@ -80,6 +80,10 @@ wire data_enabled;
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wire _fifo_ready;
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assign fifo_ready = _fifo_ready | ~enabled;
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wire [DATA_WIDTH-1:0] dout_s;
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wire valid_s;
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wire underflow_s;
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wire xfer_req_s;
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reg en_d1;
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wire data_ready;
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wire data_valid;
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@ -93,9 +97,9 @@ begin
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end
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end
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assign underflow = en_d1 & (~data_valid | ~enable);
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assign underflow_s = en_d1 & (~data_valid | ~enable);
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assign data_ready = en_d1 & (data_valid | ~enable);
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assign valid = en_d1 & data_valid & enable;
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assign valid_s = en_d1 & data_valid & enable;
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dmac_data_mover # (
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.ID_WIDTH(ID_WIDTH),
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@ -109,7 +113,7 @@ dmac_data_mover # (
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.enable(enable),
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.enabled(data_enabled),
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.sync_id(sync_id),
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.xfer_req(xfer_req),
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.xfer_req(xfer_req_s),
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.request_id(request_id),
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.response_id(data_id),
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@ -124,10 +128,30 @@ dmac_data_mover # (
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.s_axi_data(fifo_data),
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.m_axi_ready(data_ready),
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.m_axi_valid(data_valid),
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.m_axi_data(dout),
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.m_axi_data(dout_s),
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.m_axi_last()
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);
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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valid <= 1'b0;
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underflow <= 1'b0;
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xfer_req <= 1'b0;
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end else begin
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valid <= valid_s;
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underflow <= underflow_s;
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xfer_req <= xfer_req_s;
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end
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end
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always @(posedge clk) begin
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if ((resetn == 1'b0) || (valid_s == 1'b0)) begin
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dout <= {DATA_WIDTH{1'b0}};
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end else begin
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dout <= dout_s;
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end
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end
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dmac_response_generator # (
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.ID_WIDTH(ID_WIDTH)
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) i_response_generator (
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