diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v
index d071cb389..10012f0a9 100755
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@@ -50,12 +50,11 @@ module axi_ad9625 (
   // dma interface
 
   adc_clk,
-  adc_dwr,
-  adc_ddata,
-  adc_dsync,
+  adc_valid,
+  adc_enable,
+  adc_data,
   adc_dovf,
   adc_dunf,
-  adc_enable,
   adc_sref,
   adc_raddr_in,
   adc_raddr_out,
@@ -86,8 +85,8 @@ module axi_ad9625 (
   parameter PCORE_DEVICE_TYPE = 0;
   parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
   parameter C_S_AXI_MIN_SIZE = 32'hffff;
-  parameter C_BASEADDR = 32'hffffffff;
-  parameter C_HIGHADDR = 32'h00000000;
+  parameter C_HIGHADDR = 32'hffffffff;
+  parameter C_BASEADDR = 32'h00000000;
 
   // jesd interface 
   // rx_clk is (line-rate/40)
@@ -98,12 +97,11 @@ module axi_ad9625 (
   // dma interface
 
   output          adc_clk;
-  output          adc_dwr;
-  output  [255:0] adc_ddata;
-  output          adc_dsync;
+  output          adc_valid;
+  output          adc_enable;
+  output  [255:0] adc_data;
   input           adc_dovf;
   input           adc_dunf;
-  output          adc_enable;
   output  [ 15:0] adc_sref;
   input   [  3:0] adc_raddr_in;
   output  [  3:0] adc_raddr_out;
@@ -132,9 +130,6 @@ module axi_ad9625 (
 
   // internal registers
 
-  reg             adc_dsync = 'd0;
-  reg             adc_dwr = 'd0;
-  reg     [255:0] adc_ddata = 'd0;
   reg     [ 31:0] up_rdata = 'd0;
   reg             up_ack = 'd0;
 
@@ -149,32 +144,21 @@ module axi_ad9625 (
   wire    [191:0] adc_data_s;
   wire            adc_or_s;
   wire            adc_status_s;
-  wire    [255:0] adc_channel_data_s;
   wire            up_adc_pn_err_s;
   wire            up_adc_pn_oos_s;
   wire            up_adc_or_s;
-  wire    [ 31:0] up_adc_channel_rdata_s;
-  wire            up_adc_channel_ack_s;
   wire            up_sel_s;
   wire            up_wr_s;
   wire    [ 13:0] up_addr_s;
   wire    [ 31:0] up_wdata_s;
-  wire    [ 31:0] up_adc_common_rdata_s;
-  wire            up_adc_common_ack_s;
+  wire    [ 31:0] up_rdata_s[0:1];
+  wire            up_ack_s[0:1];
 
   // signal name changes
 
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
 
-  // adc channels - dma interface
-
-  always @(posedge adc_clk) begin
-    adc_dsync <= 1'b1;
-    adc_dwr <= 1'b1;
-    adc_ddata <= adc_channel_data_s;
-  end
-
   // processor read interface
 
   always @(negedge up_rstn or posedge up_clk) begin
@@ -182,13 +166,15 @@ module axi_ad9625 (
       up_rdata <= 'd0;
       up_ack <= 'd0;
     end else begin
-      up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_s;
-      up_ack <= up_adc_common_ack_s | up_adc_channel_ack_s;
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1];
+      up_ack <= up_ack_s[0] | up_ack_s[1] ;
     end
   end
 
   // main (device interface)
 
+  assign adc_valid = 1'b1;
+
   axi_ad9625_if #(.PCORE_ID(PCORE_ID)) i_if (
     .rx_clk (rx_clk),
     .rx_data (rx_data),
@@ -208,8 +194,8 @@ module axi_ad9625 (
     .adc_rst (adc_rst),
     .adc_data (adc_data_s),
     .adc_or (adc_or_s),
+    .adc_dfmt_data (adc_data),
     .adc_enable (adc_enable),
-    .adc_dfmt_data (adc_channel_data_s),
     .up_adc_pn_err (up_adc_pn_err_s),
     .up_adc_pn_oos (up_adc_pn_oos_s),
     .up_adc_or (up_adc_or_s),
@@ -219,8 +205,8 @@ module axi_ad9625 (
     .up_wr (up_wr_s),
     .up_addr (up_addr_s),
     .up_wdata (up_wdata_s),
-    .up_rdata (up_adc_channel_rdata_s),
-    .up_ack (up_adc_channel_ack_s));
+    .up_rdata (up_rdata_s[0]),
+    .up_ack (up_ack_s[0]));
 
   // common processor control
 
@@ -232,12 +218,12 @@ module axi_ad9625 (
     .adc_ddr_edgesel (),
     .adc_pin_mode (),
     .adc_status (adc_status_s),
-    .adc_status_pn_err (up_adc_pn_err_s),
-    .adc_status_pn_oos (up_adc_pn_oos_s),
-    .adc_status_or (up_adc_or_s),
     .adc_status_ovf (adc_dovf),
     .adc_status_unf (adc_dunf),
     .adc_clk_ratio (32'd1),
+    .up_status_pn_err (up_adc_pn_err_s),
+    .up_status_pn_oos (up_adc_pn_oos_s),
+    .up_status_or (up_adc_or_s),
     .delay_clk (1'b0),
     .delay_rst (),
     .delay_sel (),
@@ -258,14 +244,16 @@ module axi_ad9625 (
     .drp_locked (1'd1),
     .up_usr_chanmax (),
     .adc_usr_chanmax (8'd1),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_sel (up_sel_s),
     .up_wr (up_wr_s),
     .up_addr (up_addr_s),
     .up_wdata (up_wdata_s),
-    .up_rdata (up_adc_common_rdata_s),
-    .up_ack (up_adc_common_ack_s));
+    .up_rdata (up_rdata_s[1]),
+    .up_ack (up_ack_s[1]));
 
   // up bus interface
 
diff --git a/library/axi_ad9625/axi_ad9625_channel.v b/library/axi_ad9625/axi_ad9625_channel.v
index ca0bad40b..88d41bdcd 100755
--- a/library/axi_ad9625/axi_ad9625_channel.v
+++ b/library/axi_ad9625/axi_ad9625_channel.v
@@ -51,8 +51,8 @@ module axi_ad9625_channel (
 
   // channel interface
 
-  adc_enable,
   adc_dfmt_data,
+  adc_enable,
   up_adc_pn_err,
   up_adc_pn_oos,
   up_adc_or,
@@ -77,8 +77,8 @@ module axi_ad9625_channel (
 
   // channel interface
 
-  output          adc_enable;
   output [255:0]  adc_dfmt_data;
+  output          adc_enable;
   output          up_adc_pn_err;
   output          up_adc_pn_oos;
   output          up_adc_or;
@@ -96,12 +96,12 @@ module axi_ad9625_channel (
 
   // internal signals
 
-  wire            adc_dfmt_se_s;
-  wire            adc_dfmt_type_s;
-  wire            adc_dfmt_enable_s;
   wire            adc_pn_oos_s;
   wire            adc_pn_err_s;
-  wire            adc_pn_type_s;
+  wire            adc_dfmt_enable_s;
+  wire            adc_dfmt_type_s;
+  wire            adc_dfmt_se_s;
+  wire    [ 3:0]  adc_pnseq_sel_s;
 
   // instantiations
 
@@ -110,7 +110,7 @@ module axi_ad9625_channel (
     .adc_data (adc_data),
     .adc_pn_oos (adc_pn_oos_s),
     .adc_pn_err (adc_pn_err_s),
-    .adc_pn_type (adc_pn_type_s));
+    .adc_pnseq_sel (adc_pnseq_sel_s));
 
   genvar n;
   generate
@@ -131,18 +131,17 @@ module axi_ad9625_channel (
     .adc_clk (adc_clk),
     .adc_rst (adc_rst),
     .adc_enable (adc_enable),
-    .adc_lb_enb (),
-    .adc_pn_sel (),
     .adc_iqcor_enb (),
     .adc_dcfilt_enb (),
     .adc_dfmt_se (adc_dfmt_se_s),
     .adc_dfmt_type (adc_dfmt_type_s),
     .adc_dfmt_enable (adc_dfmt_enable_s),
-    .adc_pn_type (adc_pn_type_s),
     .adc_dcfilt_offset (),
     .adc_dcfilt_coeff (),
     .adc_iqcor_coeff_1 (),
     .adc_iqcor_coeff_2 (),
+    .adc_pnseq_sel (adc_pnseq_sel_s),
+    .adc_data_sel (),
     .adc_pn_err (adc_pn_err_s),
     .adc_pn_oos (adc_pn_oos_s),
     .adc_or (adc_or),
diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl
index 185038ee6..b3f564d1c 100755
--- a/library/axi_ad9625/axi_ad9625_ip.tcl
+++ b/library/axi_ad9625/axi_ad9625_ip.tcl
@@ -7,6 +7,7 @@ adi_ip_create axi_ad9625
 adi_ip_files axi_ad9625 [list \
   "$ad_hdl_dir/library/common/ad_rst.v" \
   "$ad_hdl_dir/library/common/ad_mem.v" \
+  "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_datafmt.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
diff --git a/library/axi_ad9625/axi_ad9625_pnmon.v b/library/axi_ad9625/axi_ad9625_pnmon.v
index 5bd9b249c..551ba0464 100755
--- a/library/axi_ad9625/axi_ad9625_pnmon.v
+++ b/library/axi_ad9625/axi_ad9625_pnmon.v
@@ -54,7 +54,7 @@ module axi_ad9625_pnmon (
 
   // processor interface PN9 (0x0), PN23 (0x1)
 
-  adc_pn_type);
+  adc_pnseq_sel);
 
   // adc interface
 
@@ -68,29 +68,16 @@ module axi_ad9625_pnmon (
 
   // processor interface PN9 (0x0), PN23 (0x1)
 
-  input           adc_pn_type;
+  input   [ 3:0]  adc_pnseq_sel;
 
   // internal registers
 
-  reg     [191:0] adc_pn_data = 'd0;
-  reg             adc_pn_match_d_1 = 'd0;
-  reg             adc_pn_match_d_0 = 'd0;
-  reg             adc_pn_match_z = 'd0;
-  reg             adc_pn_err = 'd0;
-  reg     [  6:0] adc_pn_oos_count = 'd0;
-  reg             adc_pn_oos = 'd0;
+  reg     [191:0] adc_pn_data_in = 'd0;
+  reg     [191:0] adc_pn_data_pn = 'd0;
 
   // internal signals
 
-  wire   [191:0]  adc_pn_data_rev_s;
-  wire   [191:0]  adc_pn_data_in_s;
-  wire            adc_pn_match_d_1_s;
-  wire            adc_pn_match_d_0_s;
-  wire            adc_pn_match_z_s;
-  wire            adc_pn_match_s;
-  wire   [191:0]  adc_pn_data_s;
-  wire            adc_pn_update_s;
-  wire            adc_pn_err_s;
+  wire   [191:0]  adc_pn_data_pn_s;
 
   // PN23 function
 
@@ -496,60 +483,43 @@ module axi_ad9625_pnmon (
     end
   endfunction
 
-  // pn sequence checking algorithm is commonly used in most applications.
-  // if oos is asserted (pn is out of sync):
-  //    the next sequence is generated from the incoming data.
-  //    if 16 sequences match consecutively, oos is cleared (de-asserted).
-  // if oos is de-asserted (pn is in sync)
-  //    the next sequence is generated from the current sequence.
-  //    if 64 sequences mismatch consecutively, oos is set (asserted).
-  // if oos is de-asserted, any spurious mismatches sets the error register.
-  // ideally, processor should make sure both oos == 0x0 and err == 0x0.
+  // pn sequence select
 
-  assign adc_pn_data_rev_s = {adc_data[ 11:  0], adc_data[ 23: 12],
-    adc_data[ 35: 24], adc_data[ 47: 36], adc_data[ 59: 48], adc_data[ 71: 60],
-    adc_data[ 83: 72], adc_data[ 95: 84], adc_data[107: 96], adc_data[119:108],
-    adc_data[131:120], adc_data[143:132], adc_data[155:144], adc_data[167:156],
-    adc_data[179:168], adc_data[191:180]};
-  assign adc_pn_data_in_s = adc_pn_data_rev_s ^ {{16{12'h800}}};
-  assign adc_pn_match_d_1_s = (adc_pn_data_in_s[191: 96] == adc_pn_data[191: 96]) ? 1'b1 : 1'b0;
-  assign adc_pn_match_d_0_s = (adc_pn_data_in_s[ 95:  0] == adc_pn_data[ 95:  0]) ? 1'b1 : 1'b0;
-  assign adc_pn_match_z_s = (adc_pn_data_in_s == 192'd0) ? 1'b0 : 1'b1;
-  assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
-  assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
-  assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
-  assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
-
-  // pn running sequence
+  assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
 
   always @(posedge adc_clk) begin
-    if (adc_pn_type == 1'b0) begin
-      adc_pn_data <= pn9(adc_pn_data_s);
+    adc_pn_data_in <= { ~adc_data[ 11], adc_data[ 10:  0],
+                        ~adc_data[ 23], adc_data[ 22: 12],
+                        ~adc_data[ 35], adc_data[ 34: 24],
+                        ~adc_data[ 47], adc_data[ 46: 36],
+                        ~adc_data[ 59], adc_data[ 58: 48],
+                        ~adc_data[ 71], adc_data[ 70: 60],
+                        ~adc_data[ 83], adc_data[ 82: 72],
+                        ~adc_data[ 95], adc_data[ 94: 84],
+                        ~adc_data[107], adc_data[106: 96],
+                        ~adc_data[119], adc_data[118:108],
+                        ~adc_data[131], adc_data[130:120],
+                        ~adc_data[143], adc_data[142:132],
+                        ~adc_data[155], adc_data[154:144],
+                        ~adc_data[167], adc_data[166:156],
+                        ~adc_data[179], adc_data[178:168],
+                        ~adc_data[191], adc_data[190:180]};
+    if (adc_pnseq_sel == 4'd0) begin
+      adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
     end else begin
-      adc_pn_data <= pn23(adc_pn_data_s);
+      adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
     end
   end
 
-  // pn oos and counters (64 to clear and set).
+  // pn oos & pn error
 
-  always @(posedge adc_clk) begin
-    adc_pn_match_d_1 <= adc_pn_match_d_1_s;
-    adc_pn_match_d_0 <= adc_pn_match_d_0_s;
-    adc_pn_match_z <= adc_pn_match_z_s;
-    adc_pn_err <= adc_pn_err_s;
-    if (adc_pn_update_s == 1'b1) begin
-      if (adc_pn_oos_count >= 16) begin
-        adc_pn_oos_count <= 'd0;
-        adc_pn_oos <= ~adc_pn_oos;
-      end else begin
-        adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
-        adc_pn_oos <= adc_pn_oos;
-      end
-    end else begin
-      adc_pn_oos_count <= 'd0;
-      adc_pn_oos <= adc_pn_oos;
-    end
-  end
+  ad_pnmon #(.DATA_WIDTH(192)) i_pnmon (
+    .adc_clk (adc_clk),
+    .adc_valid_in (1'b1),
+    .adc_data_in (adc_pn_data_in),
+    .adc_data_pn (adc_pn_data_pn),
+    .adc_pn_oos (adc_pn_oos),
+    .adc_pn_err (adc_pn_err));
 
 endmodule