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adi_project_intel: set_interconnect_requirment command is deprecated 

Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
main
Istvan Csomortani 2019-09-09 14:12:00 +01:00 committed by Adrian Costina
parent a39fa831d0
commit f3142a6a7a
2 changed files with 3 additions and 18 deletions
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15
projects/daq2/a10gx/system_qsys.tcl
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@ -5,18 +5,3 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/intel/dacfifo_qsys.tcl
source ../common/daq2_qsys.tcl
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src0/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_data_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src1/sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_instruction_master_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src2/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src3/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src4/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_wr_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src5/sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_rd_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src6/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_tx_mm_read_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|rsp_demux_021.src7/sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.sink} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_rx_mm_write_rsp_width_adapter.src/async_fifo_011.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_cpu_instruction_master_rsp_width_adapter.src/crosser_003.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_wr_rsp_width_adapter.src/async_fifo_006.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9680_dma_m_dest_axi_rd_rsp_width_adapter.src/async_fifo_007.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_wr_rsp_width_adapter.src/async_fifo_008.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_axi_ad9144_dma_m_src_axi_rd_rsp_width_adapter.src/async_fifo_009.in} {qsys_mm.postTransform.pipelineCount} {1}
set_interconnect_requirement {mm_interconnect_0|sys_ddr3_cntrl_ctrl_amm_0_to_sys_ethernet_dma_tx_mm_read_rsp_width_adapter.src/async_fifo_010.in} {qsys_mm.postTransform.pipelineCount} {1}

6
projects/scripts/adi_project_intel.tcl
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@ -116,9 +116,9 @@ proc adi_project {project_name {parameter_list {}}} {
puts $QFILE "set_project_property DEVICE $device"
puts $QFILE "foreach {param value} {$parameter_list} { set ad_project_params(\$param) \$value }"
puts $QFILE "source system_qsys.tcl"
puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.clockCrossingAdapter} {AUTO}"
puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.burstAdapterImplementation} {PER_BURST_TYPE_CONVERTER}"
puts $QFILE "set_interconnect_requirement {\$system} {qsys_mm.maxAdditionalLatency} {4}"
puts $QFILE "set_domain_assignment {\$system} {qsys_mm.maxAdditionalLatency} {4}"
puts $QFILE "set_domain_assignment {\$system} {qsys_mm.clockCrossingAdapter} {AUTO}"
puts $QFILE "set_domain_assignment {\$system} {qsys_mm.burstAdapterImplementation} {PER_BURST_TYPE_CONVERTER}"
puts $QFILE "save_system {system_bd.qsys}"
close $QFILE