adi_ip_alt.tcl: Delete deprecated procs
parent
17afb4d9c5
commit
f2b3b7f493
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@ -71,25 +71,6 @@ proc ad_conduit {if_name if_port port dir width} {
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add_interface_port $if_name $port $if_port $dir $width
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}
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proc ad_generate_module_inst { inst_name mark source_file target_file } {
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set fp_source [open $source_file "r"]
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set fp_target [open $target_file "w+"]
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fconfigure $fp_source -buffering line
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while { [gets $fp_source data] >= 0 } {
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# update the required module name
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regsub $inst_name $data "&_$mark" data
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puts $data
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puts $fp_target $data
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}
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close $fp_source
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close $fp_target
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}
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###################################################################################################
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###################################################################################################
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@ -395,32 +376,3 @@ proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} {
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###################################################################################################
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###################################################################################################
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proc ad_ip_modfile {ifile ofile flist} {
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global ad_hdl_dir
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set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r]
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set dstfile [open ${ofile} w]
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regsub {\..$} $ifile {} imodule
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regsub {\..$} $ofile {} omodule
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while {[gets $srcfile srcline] >= 0} {
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regsub __${imodule}__ $srcline $omodule dstline
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set index 0
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foreach fword $flist {
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incr index
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regsub __${imodule}_${index}__ $dstline $fword dstline
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}
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puts $dstfile $dstline
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}
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close $srcfile
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close $dstfile
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ad_ip_addfile ad_ip_addfile $ofile
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}
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###################################################################################################
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###################################################################################################
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