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daq3: Delete redundant timing constraint 

Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
main
Istvan Csomortani 2020-03-16 08:50:46 +00:00 committed by Adrian Costina
parent 1c907b9248
commit f1a0946a5d
2 changed files with 0 additions and 13 deletions
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7
projects/daq3/a10gx/system_constr.sdc
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@ -19,10 +19,3 @@ set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_re
set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_wen} ]
set_false_path -from * -to [get_ports {flash_resetn}]
set current_exe $::TimeQuestInfo(nameofexecutable)
if { $current_exe == "quartus_fit" } {
set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl_core_usr_clk}] -to [get_clocks {i_system_bd|sys_ddr3_cntrl_core_usr_clk}] 3
set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl_phy_clk_l_0}] -to [get_clocks {i_system_bd|sys_ddr3_cntrl_core_usr_clk}] 3
set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl_phy_clk_l_1}] -to [get_clocks {i_system_bd|sys_ddr3_cntrl_core_usr_clk}] 3
set_max_delay -from [get_clocks {i_system_bd|ad9680_jesd204|link_pll|outclk0}] -to [get_clocks {i_system_bd|ad9680_jesd204|link_pll|outclk0}] 3
}

6
projects/daq3/a10gx/system_project.tcl
View File

@ -98,11 +98,5 @@ set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_
set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P
set_location_assignment PIN_AW14 -to spi_dir ; ## C11 FMCA_LA06_N
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -to "system_bd:i_system_bd|util_adcfifo:ad9680_adcfifo"
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS OFF -to "system_bd:i_system_bd|system_bd_altera_mm_interconnect_161_mcfxx2a:mm_interconnect_0"
# set optimization to get a better timing closure
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
execute_flow -compile