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adrv9371x: zcu102: Fix QPLL feedback divider 

The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2017-11-10 17:03:29 +01:00
parent 45f2fbf3c0
commit f181e037cc
1 changed files with 1 additions and 1 deletions
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2
projects/adrv9371x/zcu102/system_bd.tcl
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@ -17,5 +17,5 @@ ad_connect sys_dma_clk sys_ps8/pl_clk2
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
ad_ip_parameter util_ad9371_xcvr CONFIG.XCVR_TYPE 2
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80
ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1