imageon_zed: Initial commit plus fix ILAs
Istvan Csomortani
parent
2937445cce
commit
f15ff45afc
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@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {1}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_hdmi_rx_dma
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ad_connect hdmi_rx_clk axi_hdmi_rx_core/hdmi_rx_clk
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@ -63,23 +63,18 @@ ad_cpu_interrupt ps-12 mb-12 axi_hdmi_rx_dma/irq
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set ila_fifo_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_fifo_dma_rx]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_DATA_DEPTH {16384}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_DATA_DEPTH {2048}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_fifo_dma_rx
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set ila_axi_dma_rx [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_axi_dma_rx]
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set_property -dict [list CONFIG.C_DATA_DEPTH {16384}] $ila_axi_dma_rx
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {32}] $ila_fifo_dma_rx
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_fifo_dma_rx
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ad_connect hdmi_rx_clk ila_fifo_dma_rx/clk
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ad_connect hdmi_rx_clk ila_axi_dma_rx/clk
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ad_connect ila_fifo_dma_rx/probe0 axi_hdmi_rx_dma/fifo_wr_sync
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ad_connect ila_fifo_dma_rx/probe1 axi_hdmi_rx_dma/fifo_wr_en
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ad_connect ila_fifo_dma_rx/probe2 axi_hdmi_rx_dma/fifo_wr_din
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ad_connect ila_fifo_dma_rx/probe3 axi_hdmi_rx_dma/fifo_wr_overflow
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ad_connect ila_axi_dma_rx/SLOT_0_AXI axi_hdmi_rx_dma/m_dest_axi
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@ -0,0 +1,4 @@
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/imageon_bd.tcl
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@ -0,0 +1,53 @@
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# fmc hdmi rx (adv7611)
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set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_clk] ; ## G2 FMC_LPC_CLK1_M2C_P
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[0]] ; ## H32 FMC_LPC_LA28_N
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set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[1]] ; ## H31 FMC_LPC_LA28_P
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set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[2]] ; ## G31 FMC_LPC_LA29_N
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[3]] ; ## C27 FMC_LPC_LA27_N
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set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[4]] ; ## D27 FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[5]] ; ## G30 FMC_LPC_LA29_P
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set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[6]] ; ## C26 FMC_LPC_LA27_P
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set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[7]] ; ## D26 FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[8]] ; ## H38 FMC_LPC_LA32_N
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set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[9]] ; ## H37 FMC_LPC_LA32_P
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set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[10]] ; ## G37 FMC_LPC_LA33_N
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set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[11]] ; ## G36 FMC_LPC_LA33_P
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[12]] ; ## H35 FMC_LPC_LA30_N
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set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[13]] ; ## H34 FMC_LPC_LA30_P
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[14]] ; ## G34 FMC_LPC_LA31_N
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_data[15]] ; ## G33 FMC_LPC_LA31_P
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_int] ; ## D08 FMC_LPC_LA01_CC_P
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# fmc hdmi tx (adv7511)
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set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_clk] ; ## G3 FMC_LPC_CLK1_M2C_N
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set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_spdif] ; ## H28 FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[0]] ; ## G28 FMC_LPC_LA25_N
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[1]] ; ## G27 FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[2]] ; ## H26 FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[3]] ; ## D24 FMC_LPC_LA23_N
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set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[4]] ; ## H25 FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[5]] ; ## G25 FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[6]] ; ## C23 FMC_LPC_LA18_CC_N
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[7]] ; ## D23 FMC_LPC_LA23_P
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[8]] ; ## G24 FMC_LPC_LA22_P
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[9]] ; ## H23 FMC_LPC_LA19_N
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set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[10]] ; ## C22 FMC_LPC_LA18_CC_P
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[11]] ; ## D21 FMC_LPC_LA17_CC_N
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[12]] ; ## H22 FMC_LPC_LA19_P
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set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[13]] ; ## G22 FMC_LPC_LA20_N
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set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[14]] ; ## D20 FMC_LPC_LA17_CC_P
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_data[15]] ; ## G21 FMC_LPC_LA20_P
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# iic pins
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set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_scl] ; ## G18 FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_sda] ; ## G19 FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_rstn] ; ## D9 FMC_LPC_LA01_CC_N
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# clock definition
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create_clock -period 6.66667 -name hdmi_rx_clk [get_ports hdmi_rx_clk]
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@ -0,0 +1,20 @@
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# load script
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set project_name imageon_zed
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adi_project_create $project_name
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adi_project_files $project_name [list "system_top.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zed/zed_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run $project_name
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@ -0,0 +1,299 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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hdmi_rx_clk,
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hdmi_rx_data,
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hdmi_rx_int,
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hdmi_tx_clk,
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hdmi_tx_data,
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hdmi_tx_spdif,
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hdmi_iic_scl,
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hdmi_iic_sda,
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hdmi_iic_rstn,
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otg_vbusoc);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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input hdmi_rx_clk;
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input [15:0] hdmi_rx_data;
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inout hdmi_rx_int;
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output hdmi_tx_clk;
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output [15:0] hdmi_tx_data;
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output hdmi_tx_spdif;
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output hdmi_iic_rstn;
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inout hdmi_iic_scl;
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inout hdmi_iic_sda;
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input otg_vbusoc;
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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// base hdmi
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assign hdmi_iic_rstn = 1'b1;
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assign hdmi_out_clk = 1'd0;
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assign hdmi_vsync = 1'd0;
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assign hdmi_hsync = 1'd0;
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assign hdmi_data_e = 1'd0;
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assign hdmi_data = 24'd0;
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assign spdif = 1'd0;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
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.dt (gpio_t[32]),
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.di (gpio_o[32]),
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.do (gpio_i[32]),
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.dio (hdmi_rx_int));
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ad_iobuf #(
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.DATA_WIDTH(32)
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) i_iobuf (
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.dt(gpio_t[31:0]),
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.di(gpio_o[31:0]),
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.do(gpio_i[31:0]),
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.dio(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_scl (
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.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.di(iic_mux_scl_o_s),
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.do(iic_mux_scl_i_s),
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.dio(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_sda (
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.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.di(iic_mux_sda_o_s),
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.do(iic_mux_sda_i_s),
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.dio(iic_mux_sda));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (),
|
||||
.hdmi_data_e (),
|
||||
.hdmi_es_data (hdmi_tx_data),
|
||||
.hdmi_hsync (),
|
||||
.hdmi_out_clk (hdmi_tx_clk),
|
||||
.hdmi_rx_clk (hdmi_rx_clk),
|
||||
.hdmi_rx_data (hdmi_rx_data),
|
||||
.hdmi_vsync (),
|
||||
.iic_imageon_scl_io (hdmi_iic_scl),
|
||||
.iic_imageon_sda_io (hdmi_iic_sda),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
.ps_intr_03 (1'b0),
|
||||
.ps_intr_04 (1'b0),
|
||||
.ps_intr_05 (1'b0),
|
||||
.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_13 (1'b0),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (hdmi_tx_spdif),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (),
|
||||
.spi0_csn_0_o (),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b0),
|
||||
.spi0_sdi_i (1'b0),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b0),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o ());
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue