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axi_pulse_gen: Update constraint file 

- add missing false paths
 - change the bus skew constraint to a false path, for some reason the
   tool does not change the path's requirement after a set_bus_skew
   constraint
main
Istvan Csomortani 2019-03-25 06:42:55 +00:00 committed by István Csomortáni
parent 3a7d0698a8
commit f1403aa593
1 changed files with 14 additions and 8 deletions
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22
library/axi_pulse_gen/axi_pulse_gen_constr.ttcl
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@ -12,25 +12,31 @@ set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
## it is constrained to a 250MHz external clock, it can be relaxed if required
## max skew must be num_of_synchronization_stages x destination_clock_period_ns
set_bus_skew -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_data_reg*}] \
8
set_bus_skew -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_data_reg*}] \
8
set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_data_reg*}] \
set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_data_reg*}] \
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/out_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
<: } :>